2018-07-21 13:41:12 +01:00
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/*
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2019-10-20 21:12:20 +01:00
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* Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
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2018-07-21 13:41:12 +01:00
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* Copyright (c) 2018, Icenowy Zheng <icenowy@aosc.io>
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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2018-10-02 00:21:49 +01:00
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#include <errno.h>
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2018-12-14 00:18:21 +00:00
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2018-10-02 00:21:49 +01:00
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#include <platform_def.h>
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2018-12-14 00:18:21 +00:00
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#include <common/debug.h>
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2019-10-21 02:50:57 +01:00
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#include <drivers/allwinner/axp.h>
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2018-12-14 00:18:21 +00:00
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#include <drivers/allwinner/sunxi_rsb.h>
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#include <lib/mmio.h>
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2018-10-02 00:21:49 +01:00
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#include <sunxi_def.h>
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#include <sunxi_mmap.h>
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2018-10-14 12:02:02 +01:00
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#include <sunxi_private.h>
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2018-07-21 13:41:12 +01:00
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2018-10-02 00:21:49 +01:00
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static enum pmic_type {
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2019-10-20 21:12:20 +01:00
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UNKNOWN,
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2018-10-02 00:21:49 +01:00
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GENERIC_H5,
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GENERIC_A64,
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2018-10-02 00:21:53 +01:00
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REF_DESIGN_H5, /* regulators controlled by GPIO pins on port L */
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2018-09-15 01:18:49 +01:00
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AXP803_RSB, /* PMIC connected via RSB on most A64 boards */
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2018-10-02 00:21:49 +01:00
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} pmic;
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2018-09-15 01:18:49 +01:00
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#define AXP803_HW_ADDR 0x3a3
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#define AXP803_RT_ADDR 0x2d
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2018-10-02 00:21:49 +01:00
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/*
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* On boards without a proper PMIC we struggle to turn off the system properly.
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* Try to turn off as much off the system as we can, to reduce power
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* consumption. This should be entered with only one core running and SMP
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* disabled.
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* This function only cares about peripherals.
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*/
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2019-10-21 02:00:27 +01:00
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static void sunxi_turn_off_soc(uint16_t socid)
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2018-07-21 13:41:12 +01:00
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{
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2018-10-02 00:21:49 +01:00
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int i;
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/** Turn off most peripherals, most importantly DRAM users. **/
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/* Keep DRAM controller running for now. */
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mmio_clrbits_32(SUNXI_CCU_BASE + 0x2c0, ~BIT_32(14));
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mmio_clrbits_32(SUNXI_CCU_BASE + 0x60, ~BIT_32(14));
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/* Contains msgbox (bit 21) and spinlock (bit 22) */
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mmio_write_32(SUNXI_CCU_BASE + 0x2c4, 0);
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mmio_write_32(SUNXI_CCU_BASE + 0x64, 0);
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mmio_write_32(SUNXI_CCU_BASE + 0x2c8, 0);
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/* Keep PIO controller running for now. */
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mmio_clrbits_32(SUNXI_CCU_BASE + 0x68, ~(BIT_32(5)));
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mmio_write_32(SUNXI_CCU_BASE + 0x2d0, 0);
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/* Contains UART0 (bit 16) */
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mmio_write_32(SUNXI_CCU_BASE + 0x2d8, 0);
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mmio_write_32(SUNXI_CCU_BASE + 0x6c, 0);
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mmio_write_32(SUNXI_CCU_BASE + 0x70, 0);
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/** Turn off DRAM controller. **/
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mmio_clrbits_32(SUNXI_CCU_BASE + 0x2c0, BIT_32(14));
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mmio_clrbits_32(SUNXI_CCU_BASE + 0x60, BIT_32(14));
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2018-07-21 13:41:12 +01:00
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2018-10-02 00:21:49 +01:00
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/** Migrate CPU and bus clocks away from the PLLs. **/
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/* AHB1: use OSC24M/1, APB1 = AHB1 / 2 */
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mmio_write_32(SUNXI_CCU_BASE + 0x54, 0x1000);
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/* APB2: use OSC24M */
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mmio_write_32(SUNXI_CCU_BASE + 0x58, 0x1000000);
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/* AHB2: use AHB1 clock */
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mmio_write_32(SUNXI_CCU_BASE + 0x5c, 0);
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/* CPU: use OSC24M */
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mmio_write_32(SUNXI_CCU_BASE + 0x50, 0x10000);
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/** Turn off PLLs. **/
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for (i = 0; i < 6; i++)
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mmio_clrbits_32(SUNXI_CCU_BASE + i * 8, BIT(31));
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switch (socid) {
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case SUNXI_SOC_H5:
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mmio_clrbits_32(SUNXI_CCU_BASE + 0x44, BIT(31));
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break;
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case SUNXI_SOC_A64:
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mmio_clrbits_32(SUNXI_CCU_BASE + 0x2c, BIT(31));
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mmio_clrbits_32(SUNXI_CCU_BASE + 0x4c, BIT(31));
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break;
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}
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}
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2018-09-15 01:18:49 +01:00
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static int rsb_init(void)
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{
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int ret;
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ret = rsb_init_controller();
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if (ret)
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return ret;
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/* Start with 400 KHz to issue the I2C->RSB switch command. */
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ret = rsb_set_bus_speed(SUNXI_OSC24M_CLK_IN_HZ, 400000);
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if (ret)
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return ret;
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/*
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* Initiate an I2C transaction to write 0x7c into register 0x3e,
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* switching the PMIC to RSB mode.
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*/
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ret = rsb_set_device_mode(0x7c3e00);
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if (ret)
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return ret;
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/* Now in RSB mode, switch to the recommended 3 MHz. */
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ret = rsb_set_bus_speed(SUNXI_OSC24M_CLK_IN_HZ, 3000000);
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if (ret)
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return ret;
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/* Associate the 8-bit runtime address with the 12-bit bus address. */
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2019-10-21 02:50:57 +01:00
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ret = rsb_assign_runtime_address(AXP803_HW_ADDR,
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AXP803_RT_ADDR);
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if (ret)
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2018-09-15 01:18:49 +01:00
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return ret;
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2019-10-21 02:50:57 +01:00
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return axp_check_id();
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2018-09-15 01:18:49 +01:00
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}
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2019-10-21 02:50:57 +01:00
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int axp_read(uint8_t reg)
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2018-09-16 11:24:05 +01:00
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{
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2019-10-21 02:50:57 +01:00
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return rsb_read(AXP803_RT_ADDR, reg);
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2018-09-16 11:24:05 +01:00
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}
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2019-10-21 02:50:57 +01:00
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int axp_write(uint8_t reg, uint8_t val)
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allwinner: PMIC: AXP803: Setup basic voltage rails
Based on the just introduced PMIC FDT framework, we check the DT for more
voltage rails that need to be setup early:
- DCDC1 is typically the main board power rail, used for I/O pins, for
instance. The PMIC's default is 3.0V, but 3.3V is what most boards use,
so this needs to be adjusted as soon as possible.
- DCDC5 is supposed to be connected to the DRAM. The AXP has some
configurable reset voltage, but some boards get that wrong, so we better
set up this here to avoid over- or under-volting.
- DLDO1,2,3 and FLDO1 mostly drive some graphics related IP, some boards
need this to be up to enable HDMI or the LCD screen, so we get screen
output in U-Boot.
To get the right setup, but still being flexible, we query the DT for
the required voltage and whether that regulator is actually used. That
gives us some robust default setup U-Boot is happy with.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2018-09-16 11:24:34 +01:00
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{
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2019-10-21 02:50:57 +01:00
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return rsb_write(AXP803_RT_ADDR, reg, val);
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2018-09-16 11:24:05 +01:00
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}
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2018-09-08 19:18:37 +01:00
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int sunxi_pmic_setup(uint16_t socid, const void *fdt)
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2018-10-02 00:21:49 +01:00
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{
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2018-09-15 01:18:49 +01:00
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int ret;
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2018-10-02 00:21:49 +01:00
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switch (socid) {
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case SUNXI_SOC_H5:
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2019-10-20 21:28:14 +01:00
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NOTICE("PMIC: Assuming H5 reference regulator design\n");
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2018-10-02 00:21:53 +01:00
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pmic = REF_DESIGN_H5;
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2019-10-20 21:28:14 +01:00
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2018-10-02 00:21:49 +01:00
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break;
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case SUNXI_SOC_A64:
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pmic = GENERIC_A64;
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2019-10-20 21:28:14 +01:00
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INFO("PMIC: Probing AXP803 on RSB\n");
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2018-09-15 01:18:49 +01:00
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ret = sunxi_init_platform_r_twi(socid, true);
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if (ret)
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return ret;
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ret = rsb_init();
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if (ret)
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return ret;
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pmic = AXP803_RSB;
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2019-10-21 02:50:57 +01:00
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axp_setup_regulators(fdt);
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2018-09-16 11:24:05 +01:00
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2018-10-02 00:21:49 +01:00
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break;
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default:
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return -ENODEV;
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}
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2018-07-21 13:41:12 +01:00
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return 0;
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}
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2018-07-22 14:52:50 +01:00
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2019-10-20 21:06:57 +01:00
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void sunxi_power_down(void)
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2018-07-22 14:52:50 +01:00
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{
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2018-10-02 00:21:49 +01:00
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switch (pmic) {
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case GENERIC_H5:
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/* Turn off as many peripherals and clocks as we can. */
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sunxi_turn_off_soc(SUNXI_SOC_H5);
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/* Turn off the pin controller now. */
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mmio_write_32(SUNXI_CCU_BASE + 0x68, 0);
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break;
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case GENERIC_A64:
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/* Turn off as many peripherals and clocks as we can. */
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sunxi_turn_off_soc(SUNXI_SOC_A64);
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/* Turn off the pin controller now. */
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mmio_write_32(SUNXI_CCU_BASE + 0x68, 0);
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2018-10-02 00:21:53 +01:00
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break;
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case REF_DESIGN_H5:
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sunxi_turn_off_soc(SUNXI_SOC_H5);
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/*
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* Switch PL pins to power off the board:
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* - PL5 (VCC_IO) -> high
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* - PL8 (PWR-STB = CPU power supply) -> low
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* - PL9 (PWR-DRAM) ->low
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* - PL10 (power LED) -> low
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* Note: Clearing PL8 will reset the board, so keep it up.
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*/
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sunxi_set_gpio_out('L', 5, 1);
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sunxi_set_gpio_out('L', 9, 0);
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sunxi_set_gpio_out('L', 10, 0);
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/* Turn off pin controller now. */
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mmio_write_32(SUNXI_CCU_BASE + 0x68, 0);
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2018-09-15 01:18:49 +01:00
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break;
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case AXP803_RSB:
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/* (Re-)init RSB in case the rich OS has disabled it. */
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sunxi_init_platform_r_twi(SUNXI_SOC_A64, true);
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rsb_init();
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2019-10-21 02:50:57 +01:00
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axp_power_off();
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2018-10-02 00:21:49 +01:00
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break;
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default:
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break;
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}
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2018-07-22 14:52:50 +01:00
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}
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