2017-10-24 10:07:35 +01:00
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/*
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2018-01-08 17:33:34 +00:00
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* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
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2017-10-24 10:07:35 +01:00
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch_helpers.h>
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#include <assert.h>
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#include <bl31.h>
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#include <context_mgmt.h>
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#include <debug.h>
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#include <errno.h>
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2018-01-08 17:33:34 +00:00
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#include <mm_svc.h>
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2017-10-24 10:07:35 +01:00
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#include <platform.h>
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#include <runtime_svc.h>
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#include <secure_partition.h>
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2018-03-21 10:49:27 +00:00
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#include <smccc.h>
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#include <smccc_helpers.h>
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2017-10-24 10:07:35 +01:00
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#include <spinlock.h>
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#include <spm_svc.h>
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#include <utils.h>
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#include <xlat_tables_v2.h>
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#include "spm_private.h"
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2018-05-23 11:40:46 +01:00
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2017-10-24 10:07:35 +01:00
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/*******************************************************************************
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* Secure Partition context information.
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******************************************************************************/
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2018-05-22 16:26:48 +01:00
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static sp_context_t sp_ctx;
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2017-10-24 10:07:35 +01:00
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/*******************************************************************************
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2018-05-23 11:40:46 +01:00
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* This function takes an SP context pointer and prepares the CPU to enter.
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2017-10-24 10:07:35 +01:00
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******************************************************************************/
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2018-05-22 16:26:48 +01:00
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static void spm_sp_prepare_enter(sp_context_t *sp_ctx)
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2017-10-24 10:07:35 +01:00
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{
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2018-05-23 11:40:46 +01:00
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assert(sp_ctx != NULL);
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2017-10-24 10:07:35 +01:00
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2018-05-23 11:40:46 +01:00
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/* Assign the context of the SP to this CPU */
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cm_set_context(&(sp_ctx->cpu_ctx), SECURE);
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2017-10-24 10:07:35 +01:00
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2018-05-23 11:40:46 +01:00
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/* Restore the context assigned above */
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2017-10-24 10:07:35 +01:00
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cm_el1_sysregs_context_restore(SECURE);
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cm_set_next_eret_context(SECURE);
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2018-05-23 11:40:46 +01:00
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/* Invalidate TLBs at EL1. */
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tlbivmalle1();
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dsbish();
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2017-10-24 10:07:35 +01:00
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}
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/*******************************************************************************
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2018-05-23 11:40:46 +01:00
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* Enter SP after preparing it with spm_sp_prepare_enter().
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2017-10-24 10:07:35 +01:00
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******************************************************************************/
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2018-05-22 16:26:48 +01:00
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static uint64_t spm_sp_enter(sp_context_t *sp_ctx)
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2017-10-24 10:07:35 +01:00
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{
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2018-05-23 11:40:46 +01:00
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/* Enter Secure Partition */
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return spm_secure_partition_enter(&sp_ctx->c_rt_ctx);
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2017-10-24 10:07:35 +01:00
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}
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/*******************************************************************************
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2018-05-23 11:40:46 +01:00
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* Jump to each Secure Partition for the first time.
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2017-10-24 10:07:35 +01:00
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******************************************************************************/
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2018-04-17 15:10:18 +01:00
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static int32_t spm_init(void)
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2017-10-24 10:07:35 +01:00
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{
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2018-05-23 11:40:46 +01:00
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uint64_t rc = 0;
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2018-05-22 16:26:48 +01:00
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sp_context_t *ctx;
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2017-10-24 10:07:35 +01:00
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2018-05-23 11:40:46 +01:00
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INFO("Secure Partition init...\n");
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2017-10-24 10:07:35 +01:00
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2018-05-23 11:40:46 +01:00
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ctx = &sp_ctx;
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2017-10-24 10:07:35 +01:00
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2018-05-23 11:40:46 +01:00
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ctx->sp_init_in_progress = 1;
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2017-10-24 10:07:35 +01:00
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2018-05-23 11:40:46 +01:00
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spm_sp_prepare_enter(ctx);
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rc |= spm_sp_enter(ctx);
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assert(rc == 0);
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2017-10-24 10:07:35 +01:00
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2018-05-23 11:40:46 +01:00
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ctx->sp_init_in_progress = 0;
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2017-10-24 10:07:35 +01:00
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2018-05-23 11:40:46 +01:00
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INFO("Secure Partition initialized.\n");
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2017-10-24 10:07:35 +01:00
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2018-05-23 11:40:46 +01:00
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return rc;
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2017-10-24 10:07:35 +01:00
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}
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/*******************************************************************************
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2018-05-23 11:40:46 +01:00
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* Initialize contexts of all Secure Partitions.
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2017-10-24 10:07:35 +01:00
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******************************************************************************/
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int32_t spm_setup(void)
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{
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2018-05-22 16:26:48 +01:00
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sp_context_t *ctx;
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2017-10-24 10:07:35 +01:00
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2018-05-23 11:40:46 +01:00
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/* Disable MMU at EL1 (initialized by BL2) */
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disable_mmu_icache_el1();
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/* Initialize context of the SP */
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INFO("Secure Partition context setup start...\n");
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ctx = &sp_ctx;
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2017-10-24 10:07:35 +01:00
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2018-05-23 11:40:46 +01:00
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/* Assign translation tables context. */
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ctx->xlat_ctx_handle = spm_get_sp_xlat_context();
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2017-10-24 10:07:35 +01:00
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2018-05-22 16:26:48 +01:00
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spm_sp_setup(ctx);
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2018-05-23 11:40:46 +01:00
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/* Register init function for deferred init. */
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2017-10-24 10:07:35 +01:00
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bl31_register_bl32_init(&spm_init);
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2018-05-23 11:40:46 +01:00
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INFO("Secure Partition setup done.\n");
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2017-10-24 10:07:35 +01:00
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return 0;
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}
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2018-05-23 11:40:46 +01:00
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/*******************************************************************************
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* Secure Partition Manager SMC handler.
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******************************************************************************/
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2017-10-24 10:07:35 +01:00
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uint64_t spm_smc_handler(uint32_t smc_fid,
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uint64_t x1,
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uint64_t x2,
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uint64_t x3,
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uint64_t x4,
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void *cookie,
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void *handle,
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uint64_t flags)
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{
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cpu_context_t *ns_cpu_context;
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unsigned int ns;
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/* Determine which security state this SMC originated from */
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ns = is_caller_non_secure(flags);
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if (ns == SMC_FROM_SECURE) {
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/* Handle SMCs from Secure world. */
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2018-05-23 11:40:46 +01:00
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assert(handle == cm_get_context(SECURE));
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/* Make next ERET jump to S-EL0 instead of S-EL1. */
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cm_set_elr_spsr_el3(SECURE, read_elr_el1(), read_spsr_el1());
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2017-10-24 10:07:35 +01:00
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switch (smc_fid) {
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2017-12-07 09:48:56 +00:00
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case SPM_VERSION_AARCH32:
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2017-10-24 10:07:35 +01:00
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SMC_RET1(handle, SPM_VERSION_COMPILED);
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case SP_EVENT_COMPLETE_AARCH64:
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2018-05-23 11:40:46 +01:00
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/* Save secure state */
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2017-10-24 10:07:35 +01:00
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cm_el1_sysregs_context_save(SECURE);
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2018-05-23 11:40:46 +01:00
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if (sp_ctx.sp_init_in_progress == 1) {
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2017-10-24 10:07:35 +01:00
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/*
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* SPM reports completion. The SPM must have
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* initiated the original request through a
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* synchronous entry into the secure
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* partition. Jump back to the original C
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* runtime context.
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*/
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2018-05-23 11:40:46 +01:00
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spm_secure_partition_exit(sp_ctx.c_rt_ctx, x1);
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/* spm_secure_partition_exit doesn't return */
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2017-10-24 10:07:35 +01:00
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}
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2018-01-08 09:59:33 +00:00
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/* Release the Secure Partition context */
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2018-05-23 11:40:46 +01:00
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spin_unlock(&(sp_ctx.lock));
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2018-01-08 09:59:33 +00:00
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2017-10-24 10:07:35 +01:00
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/*
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* This is the result from the Secure partition of an
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* earlier request. Copy the result into the non-secure
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2018-05-23 11:40:46 +01:00
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* context and return to the non-secure state.
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2017-10-24 10:07:35 +01:00
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*/
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/* Get a reference to the non-secure context */
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ns_cpu_context = cm_get_context(NON_SECURE);
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2018-04-17 15:10:18 +01:00
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assert(ns_cpu_context != NULL);
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2017-10-24 10:07:35 +01:00
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/* Restore non-secure state */
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cm_el1_sysregs_context_restore(NON_SECURE);
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cm_set_next_eret_context(NON_SECURE);
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/* Return to normal world */
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SMC_RET1(ns_cpu_context, x1);
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2017-12-01 14:12:43 +00:00
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case SP_MEMORY_ATTRIBUTES_GET_AARCH64:
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INFO("Received SP_MEMORY_ATTRIBUTES_GET_AARCH64 SMC\n");
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2017-10-24 10:07:35 +01:00
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2018-05-23 11:40:46 +01:00
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if (sp_ctx.sp_init_in_progress == 0) {
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2017-12-01 14:12:43 +00:00
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WARN("SP_MEMORY_ATTRIBUTES_GET_AARCH64 is available at boot time only\n");
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2017-10-24 10:07:35 +01:00
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SMC_RET1(handle, SPM_NOT_SUPPORTED);
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}
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2018-05-23 11:40:46 +01:00
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SMC_RET1(handle,
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spm_memory_attributes_get_smc_handler(
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&sp_ctx, x1));
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2017-10-24 10:07:35 +01:00
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2017-12-01 14:12:43 +00:00
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case SP_MEMORY_ATTRIBUTES_SET_AARCH64:
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INFO("Received SP_MEMORY_ATTRIBUTES_SET_AARCH64 SMC\n");
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2017-10-24 10:07:35 +01:00
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2018-05-23 11:40:46 +01:00
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if (sp_ctx.sp_init_in_progress == 0) {
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2017-12-01 14:12:43 +00:00
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WARN("SP_MEMORY_ATTRIBUTES_SET_AARCH64 is available at boot time only\n");
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2017-10-24 10:07:35 +01:00
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SMC_RET1(handle, SPM_NOT_SUPPORTED);
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}
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2018-05-23 11:40:46 +01:00
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SMC_RET1(handle,
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spm_memory_attributes_set_smc_handler(
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&sp_ctx, x1, x2, x3));
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2017-10-24 10:07:35 +01:00
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default:
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break;
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}
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} else {
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/* Handle SMCs from Non-secure world. */
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switch (smc_fid) {
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2018-01-08 17:33:34 +00:00
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case MM_VERSION_AARCH32:
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SMC_RET1(handle, MM_VERSION_COMPILED);
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2017-10-24 10:07:35 +01:00
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2017-12-01 09:44:21 +00:00
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case MM_COMMUNICATE_AARCH32:
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case MM_COMMUNICATE_AARCH64:
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2017-12-07 09:48:56 +00:00
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{
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uint64_t mm_cookie = x1;
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uint64_t comm_buffer_address = x2;
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uint64_t comm_size_address = x3;
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/* Cookie. Reserved for future use. It must be zero. */
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2018-04-17 15:10:18 +01:00
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if (mm_cookie != 0U) {
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2017-12-07 09:48:56 +00:00
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ERROR("MM_COMMUNICATE: cookie is not zero\n");
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SMC_RET1(handle, SPM_INVALID_PARAMETER);
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}
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2018-04-17 15:10:18 +01:00
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if (comm_buffer_address == 0U) {
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2017-12-07 09:48:56 +00:00
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ERROR("MM_COMMUNICATE: comm_buffer_address is zero\n");
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SMC_RET1(handle, SPM_INVALID_PARAMETER);
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}
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2018-04-17 15:10:18 +01:00
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if (comm_size_address != 0U) {
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2017-12-07 09:48:56 +00:00
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VERBOSE("MM_COMMUNICATE: comm_size_address is not 0 as recommended.\n");
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}
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2017-10-24 10:07:35 +01:00
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/* Save the Normal world context */
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cm_el1_sysregs_context_save(NON_SECURE);
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2018-01-08 09:59:33 +00:00
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/* Lock the Secure Partition context. */
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spin_lock(&sp_ctx.lock);
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2018-05-23 11:40:46 +01:00
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/* Jump to the Secure Partition. */
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spm_sp_prepare_enter(&sp_ctx);
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2017-10-24 10:07:35 +01:00
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2018-05-23 11:40:46 +01:00
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SMC_RET4(&(sp_ctx.cpu_ctx), smc_fid,
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comm_buffer_address, comm_size_address,
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plat_my_core_pos());
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2017-12-07 09:48:56 +00:00
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}
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2017-10-24 10:07:35 +01:00
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2017-12-01 14:12:43 +00:00
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case SP_MEMORY_ATTRIBUTES_GET_AARCH64:
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case SP_MEMORY_ATTRIBUTES_SET_AARCH64:
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2017-10-24 10:07:35 +01:00
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/* SMC interfaces reserved for secure callers. */
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SMC_RET1(handle, SPM_NOT_SUPPORTED);
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default:
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break;
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}
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}
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SMC_RET1(handle, SMC_UNK);
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}
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