2016-01-07 16:52:49 +00:00
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/*
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2019-02-11 13:34:15 +00:00
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* Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
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2016-01-07 16:52:49 +00:00
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*
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2017-05-03 09:38:09 +01:00
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* SPDX-License-Identifier: BSD-3-Clause
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2016-01-07 16:52:49 +00:00
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*/
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2018-11-08 10:20:19 +00:00
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#ifndef CORTEX_A35_H
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#define CORTEX_A35_H
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2016-01-07 16:52:49 +00:00
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2019-02-11 13:34:15 +00:00
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#include <lib/utils_def.h>
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2016-01-07 16:52:49 +00:00
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/* Cortex-A35 Main ID register for revision 0 */
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2019-02-11 13:34:15 +00:00
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#define CORTEX_A35_MIDR U(0x410FD040)
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2016-01-07 16:52:49 +00:00
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/*******************************************************************************
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* CPU Extended Control register specific definitions.
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* CPUECTLR_EL1 is an implementation-specific register.
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******************************************************************************/
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#define CORTEX_A35_CPUECTLR_EL1 S3_1_C15_C2_1
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2019-02-11 13:34:15 +00:00
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#define CORTEX_A35_CPUECTLR_SMPEN_BIT (ULL(1) << 6)
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2016-01-07 16:52:49 +00:00
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2019-04-05 16:25:25 +01:00
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/*******************************************************************************
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* CPU Auxiliary Control register specific definitions.
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******************************************************************************/
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#define CORTEX_A35_CPUACTLR_EL1 S3_1_C15_C2_0
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#define CORTEX_A35_CPUACTLR_EL1_ENDCCASCI (ULL(1) << 44)
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2018-11-08 10:20:19 +00:00
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#endif /* CORTEX_A35_H */
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