2018-07-21 13:41:12 +01:00
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/*
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* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2018, Icenowy Zheng <icenowy@aosc.io>
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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2018-07-22 14:52:50 +01:00
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#include <arch_helpers.h>
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2018-07-21 13:41:12 +01:00
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#include <debug.h>
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2018-07-22 14:30:14 +01:00
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#include <delay_timer.h>
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#include <errno.h>
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#include <mmio.h>
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#include <mentor/mi2cv.h>
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#include <string.h>
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#include <sunxi_mmap.h>
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#define AXP805_ADDR 0x36
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#define AXP805_ID 0x03
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enum pmic_type {
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NO_PMIC,
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AXP805,
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};
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enum pmic_type pmic;
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static int sunxi_init_r_i2c(void)
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{
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uint32_t reg;
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/* switch pins PL0 and PL1 to I2C */
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2018-09-09 00:38:19 +01:00
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reg = mmio_read_32(SUNXI_R_PIO_BASE + 0x00);
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2018-07-22 14:30:14 +01:00
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mmio_write_32(SUNXI_R_PIO_BASE + 0x00, (reg & ~0xff) | 0x33);
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/* level 2 drive strength */
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reg = mmio_read_32(SUNXI_R_PIO_BASE + 0x14);
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mmio_write_32(SUNXI_R_PIO_BASE + 0x14, (reg & ~0x0f) | 0xa);
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/* set both ports to pull-up */
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reg = mmio_read_32(SUNXI_R_PIO_BASE + 0x1c);
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mmio_write_32(SUNXI_R_PIO_BASE + 0x1c, (reg & ~0x0f) | 0x5);
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/* assert & de-assert reset of R_I2C */
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reg = mmio_read_32(SUNXI_R_PRCM_BASE + 0x19c);
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2018-09-09 00:38:19 +01:00
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mmio_write_32(SUNXI_R_PRCM_BASE + 0x19c, reg & ~BIT(16));
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mmio_write_32(SUNXI_R_PRCM_BASE + 0x19c, reg | BIT(16));
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2018-07-22 14:30:14 +01:00
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/* un-gate R_I2C clock */
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2018-09-09 00:38:19 +01:00
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mmio_write_32(SUNXI_R_PRCM_BASE + 0x19c, reg | BIT(16) | BIT(0));
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2018-07-22 14:30:14 +01:00
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/* call mi2cv driver */
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i2c_init((void *)SUNXI_R_I2C_BASE);
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return 0;
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}
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int axp_i2c_read(uint8_t chip, uint8_t reg, uint8_t *val)
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{
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int ret;
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ret = i2c_write(chip, 0, 0, ®, 1);
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if (ret)
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return ret;
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return i2c_read(chip, 0, 0, val, 1);
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}
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int axp_i2c_write(uint8_t chip, uint8_t reg, uint8_t val)
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{
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return i2c_write(chip, reg, 1, &val, 1);
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}
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static int axp805_probe(void)
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{
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int ret;
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uint8_t val;
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ret = axp_i2c_write(AXP805_ADDR, 0xff, 0x0);
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if (ret) {
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ERROR("PMIC: Cannot put AXP805 to master mode.\n");
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return -EPERM;
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}
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ret = axp_i2c_read(AXP805_ADDR, AXP805_ID, &val);
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if (!ret && ((val & 0xcf) == 0x40))
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NOTICE("PMIC: AXP805 detected\n");
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else if (ret) {
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ERROR("PMIC: Cannot communicate with AXP805.\n");
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return -EPERM;
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} else {
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ERROR("PMIC: Non-AXP805 chip attached at AXP805's address.\n");
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return -EINVAL;
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}
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return 0;
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}
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2018-07-21 13:41:12 +01:00
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int sunxi_pmic_setup(void)
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{
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2018-07-22 14:30:14 +01:00
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int ret;
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sunxi_init_r_i2c();
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NOTICE("PMIC: Probing AXP805\n");
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pmic = AXP805;
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ret = axp805_probe();
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if (ret)
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pmic = NO_PMIC;
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else
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pmic = AXP805;
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2018-07-21 13:41:12 +01:00
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return 0;
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}
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2018-07-22 14:52:50 +01:00
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void __dead2 sunxi_power_down(void)
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{
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uint8_t val;
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switch (pmic) {
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case AXP805:
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val = 0x26; /* Default value for REG 32H */
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axp_i2c_read(AXP805_ADDR, 0x32, &val);
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val |= 0x80;
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axp_i2c_write(AXP805_ADDR, 0x32, val);
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break;
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default:
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break;
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}
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udelay(1000);
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ERROR("PSCI: Cannot communicate with PMIC, halting\n");
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wfi();
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panic();
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}
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