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arm-trusted-firmware/plat/renesas/rcar/include/registers/lifec_registers.h

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rcar-gen3: initial commit for the rcar-gen3 boards Reference code: ============== rar_gen3: IPL and Secure Monitor Rev1.0.22 https://github.com/renesas-rcar/arm-trusted-firmware [rcar_gen3] Author: Takuya Sakata <takuya.sakata.wz@bp.renesas.com> Date: Thu Aug 30 21:26:41 2018 +0900 Update IPL and Secure Monitor Rev1.0.22 General Information: =================== This port has been tested on the Salvator-X Soc_id r8a7795 revision ES1.1 (uses an SPD). Build Tested: ------------- ATFW_OPT="LSI=H3 RCAR_DRAM_SPLIT=1 RCAR_LOSSY_ENABLE=1" MBEDTLS_DIR=$mbedtls $ make clean bl2 bl31 rcar PLAT=rcar ${ATFW_OPT} SPD=opteed Other dependencies: ------------------ * mbed_tls: git@github.com:ARMmbed/mbedtls.git [devel] Merge: 68dbc94 f34a4c1 Author: Simon Butcher <simon.butcher@arm.com> Date: Thu Aug 30 00:57:28 2018 +0100 * optee_os: https://github.com/BayLibre/optee_os Until it gets merged into OP-TEE, the port requires Renesas' Trusted Environment with a modification to support power management. Author: Jorge Ramirez-Ortiz <jramirez@baylibre.com> Date: Thu Aug 30 16:49:49 2018 +0200 plat-rcar: cpu-suspend: handle the power level Signed-off-by: Jorge Ramirez-Ortiz <jramirez@baylibre.com> * u-boot: The port has beent tested using mainline uboot. Author: Fabio Estevam <festevam@gmail.com> Date: Tue Sep 4 10:23:12 2018 -0300 *linux: The port has beent tested using mainline kernel. Author: Linus Torvalds <torvalds@linux-foundation.org> Date: Sun Sep 16 11:52:37 2018 -0700 Linux 4.19-rc4 Overview --------- BOOTROM starts the cpu at EL3; In this port BL2 will therefore be entered at this exception level (the Renesas' ATF reference tree [1] resets into EL1 before entering BL2 - see its bl2.ld.S) BL2 initializes DDR (and i2c to talk to the PMIC on some platforms) before determining the boot reason (cold or warm). During suspend all CPUs are switched off and the DDR is put in backup mode (some kind of self-refresh mode). This means that BL2 is always entered in a cold boot scenario. Once BL2 boots, it determines the boot reason, writes it to shared memory (BOOT_KIND_BASE) together with the BL31 parameters (PARAMS_BASE) and jumps to BL31. To all effects, BL31 is as if it is being entered in reset mode since it still needs to initialize the rest of the cores; this is the reason behind using direct shared memory access to BOOT_KIND_BASE and PARAMS_BASE instead of using registers to get to those locations (see el3_common_macros.S and bl31_entrypoint.S for the RESET_TO_BL31 use case). Depending on the boot reason BL31 initializes the rest of the cores: in case of suspend, it uses a MBOX memory region to recover the program counters. [1] https://github.com/renesas-rcar/arm-trusted-firmware Tests ----- * cpuidle ------- enable kernel's cpuidle arm_idle driver and boot * system suspend -------------- $ cat suspend.sh #!/bin/bash i2cset -f -y 7 0x30 0x20 0x0F read -p "Switch off SW23 and press return " foo echo mem > /sys/power/state * cpu hotplug: ------------ $ cat offline.sh #!/bin/bash nbr=$1 echo 0 > /sys/devices/system/cpu/cpu$nbr/online printf "ONLINE: " && cat /sys/devices/system/cpu/online printf "OFFLINE: " && cat /sys/devices/system/cpu/offline $ cat online.sh #!/bin/bash nbr=$1 echo 1 > /sys/devices/system/cpu/cpu$nbr/online printf "ONLINE: " && cat /sys/devices/system/cpu/online printf "OFFLINE: " && cat /sys/devices/system/cpu/offline Signed-off-by: ldts <jramirez@baylibre.com>
2018-09-23 08:36:13 +01:00
/*
* Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
Standardise header guards across codebase All identifiers, regardless of use, that start with two underscores are reserved. This means they can't be used in header guards. The style that this project is now to use the full name of the file in capital letters followed by 'H'. For example, for a file called "uart_example.h", the header guard is UART_EXAMPLE_H. The exceptions are files that are imported from other projects: - CryptoCell driver - dt-bindings folders - zlib headers Change-Id: I50561bf6c88b491ec440d0c8385c74650f3c106e Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-11-08 10:20:19 +00:00
#ifndef LIFEC_REGISTERS_H
#define LIFEC_REGISTERS_H
rcar-gen3: initial commit for the rcar-gen3 boards Reference code: ============== rar_gen3: IPL and Secure Monitor Rev1.0.22 https://github.com/renesas-rcar/arm-trusted-firmware [rcar_gen3] Author: Takuya Sakata <takuya.sakata.wz@bp.renesas.com> Date: Thu Aug 30 21:26:41 2018 +0900 Update IPL and Secure Monitor Rev1.0.22 General Information: =================== This port has been tested on the Salvator-X Soc_id r8a7795 revision ES1.1 (uses an SPD). Build Tested: ------------- ATFW_OPT="LSI=H3 RCAR_DRAM_SPLIT=1 RCAR_LOSSY_ENABLE=1" MBEDTLS_DIR=$mbedtls $ make clean bl2 bl31 rcar PLAT=rcar ${ATFW_OPT} SPD=opteed Other dependencies: ------------------ * mbed_tls: git@github.com:ARMmbed/mbedtls.git [devel] Merge: 68dbc94 f34a4c1 Author: Simon Butcher <simon.butcher@arm.com> Date: Thu Aug 30 00:57:28 2018 +0100 * optee_os: https://github.com/BayLibre/optee_os Until it gets merged into OP-TEE, the port requires Renesas' Trusted Environment with a modification to support power management. Author: Jorge Ramirez-Ortiz <jramirez@baylibre.com> Date: Thu Aug 30 16:49:49 2018 +0200 plat-rcar: cpu-suspend: handle the power level Signed-off-by: Jorge Ramirez-Ortiz <jramirez@baylibre.com> * u-boot: The port has beent tested using mainline uboot. Author: Fabio Estevam <festevam@gmail.com> Date: Tue Sep 4 10:23:12 2018 -0300 *linux: The port has beent tested using mainline kernel. Author: Linus Torvalds <torvalds@linux-foundation.org> Date: Sun Sep 16 11:52:37 2018 -0700 Linux 4.19-rc4 Overview --------- BOOTROM starts the cpu at EL3; In this port BL2 will therefore be entered at this exception level (the Renesas' ATF reference tree [1] resets into EL1 before entering BL2 - see its bl2.ld.S) BL2 initializes DDR (and i2c to talk to the PMIC on some platforms) before determining the boot reason (cold or warm). During suspend all CPUs are switched off and the DDR is put in backup mode (some kind of self-refresh mode). This means that BL2 is always entered in a cold boot scenario. Once BL2 boots, it determines the boot reason, writes it to shared memory (BOOT_KIND_BASE) together with the BL31 parameters (PARAMS_BASE) and jumps to BL31. To all effects, BL31 is as if it is being entered in reset mode since it still needs to initialize the rest of the cores; this is the reason behind using direct shared memory access to BOOT_KIND_BASE and PARAMS_BASE instead of using registers to get to those locations (see el3_common_macros.S and bl31_entrypoint.S for the RESET_TO_BL31 use case). Depending on the boot reason BL31 initializes the rest of the cores: in case of suspend, it uses a MBOX memory region to recover the program counters. [1] https://github.com/renesas-rcar/arm-trusted-firmware Tests ----- * cpuidle ------- enable kernel's cpuidle arm_idle driver and boot * system suspend -------------- $ cat suspend.sh #!/bin/bash i2cset -f -y 7 0x30 0x20 0x0F read -p "Switch off SW23 and press return " foo echo mem > /sys/power/state * cpu hotplug: ------------ $ cat offline.sh #!/bin/bash nbr=$1 echo 0 > /sys/devices/system/cpu/cpu$nbr/online printf "ONLINE: " && cat /sys/devices/system/cpu/online printf "OFFLINE: " && cat /sys/devices/system/cpu/offline $ cat online.sh #!/bin/bash nbr=$1 echo 1 > /sys/devices/system/cpu/cpu$nbr/online printf "ONLINE: " && cat /sys/devices/system/cpu/online printf "OFFLINE: " && cat /sys/devices/system/cpu/offline Signed-off-by: ldts <jramirez@baylibre.com>
2018-09-23 08:36:13 +01:00
#define LIFEC_SEC_BASE (0xE6110000U)
#define SEC_SRC (LIFEC_SEC_BASE + 0x0008U)
#define SEC_SEL0 (LIFEC_SEC_BASE + 0x0030U)
#define SEC_SEL1 (LIFEC_SEC_BASE + 0x0034U)
#define SEC_SEL2 (LIFEC_SEC_BASE + 0x0038U)
#define SEC_SEL3 (LIFEC_SEC_BASE + 0x003CU)
#define SEC_SEL4 (LIFEC_SEC_BASE + 0x0058U)
#define SEC_SEL5 (LIFEC_SEC_BASE + 0x005CU)
#define SEC_SEL6 (LIFEC_SEC_BASE + 0x0060U)
#define SEC_SEL7 (LIFEC_SEC_BASE + 0x0064U)
#define SEC_SEL8 (LIFEC_SEC_BASE + 0x0068U)
#define SEC_SEL9 (LIFEC_SEC_BASE + 0x006CU)
#define SEC_SEL10 (LIFEC_SEC_BASE + 0x0070U)
#define SEC_SEL11 (LIFEC_SEC_BASE + 0x0074U)
#define SEC_SEL12 (LIFEC_SEC_BASE + 0x0078U)
#define SEC_SEL13 (LIFEC_SEC_BASE + 0x007CU)
#define SEC_SEL14 (LIFEC_SEC_BASE + 0x0080U)
#define SEC_SEL15 (LIFEC_SEC_BASE + 0x0084U)
#define SEC_GRP0CR0 (LIFEC_SEC_BASE + 0x0138U)
#define SEC_GRP1CR0 (LIFEC_SEC_BASE + 0x013CU)
#define SEC_GRP0CR1 (LIFEC_SEC_BASE + 0x0140U)
#define SEC_GRP1CR1 (LIFEC_SEC_BASE + 0x0144U)
#define SEC_GRP0CR2 (LIFEC_SEC_BASE + 0x0148U)
#define SEC_GRP1CR2 (LIFEC_SEC_BASE + 0x014CU)
#define SEC_GRP0CR3 (LIFEC_SEC_BASE + 0x0150U)
#define SEC_GRP1CR3 (LIFEC_SEC_BASE + 0x0154U)
#define SEC_GRP0COND0 (LIFEC_SEC_BASE + 0x0158U)
#define SEC_GRP1COND0 (LIFEC_SEC_BASE + 0x015CU)
#define SEC_GRP0COND1 (LIFEC_SEC_BASE + 0x0160U)
#define SEC_GRP1COND1 (LIFEC_SEC_BASE + 0x0164U)
#define SEC_GRP0COND2 (LIFEC_SEC_BASE + 0x0168U)
#define SEC_GRP1COND2 (LIFEC_SEC_BASE + 0x016CU)
#define SEC_GRP0COND3 (LIFEC_SEC_BASE + 0x0170U)
#define SEC_GRP1COND3 (LIFEC_SEC_BASE + 0x0174U)
#define SEC_GRP0COND4 (LIFEC_SEC_BASE + 0x0178U)
#define SEC_GRP1COND4 (LIFEC_SEC_BASE + 0x017CU)
#define SEC_GRP0COND5 (LIFEC_SEC_BASE + 0x0180U)
#define SEC_GRP1COND5 (LIFEC_SEC_BASE + 0x0184U)
#define SEC_GRP0COND6 (LIFEC_SEC_BASE + 0x0188U)
#define SEC_GRP1COND6 (LIFEC_SEC_BASE + 0x018CU)
#define SEC_GRP0COND7 (LIFEC_SEC_BASE + 0x0190U)
#define SEC_GRP1COND7 (LIFEC_SEC_BASE + 0x0194U)
#define SEC_GRP0COND8 (LIFEC_SEC_BASE + 0x0198U)
#define SEC_GRP1COND8 (LIFEC_SEC_BASE + 0x019CU)
#define SEC_GRP0COND9 (LIFEC_SEC_BASE + 0x01A0U)
#define SEC_GRP1COND9 (LIFEC_SEC_BASE + 0x01A4U)
#define SEC_GRP0COND10 (LIFEC_SEC_BASE + 0x01A8U)
#define SEC_GRP1COND10 (LIFEC_SEC_BASE + 0x01ACU)
#define SEC_GRP0COND11 (LIFEC_SEC_BASE + 0x01B0U)
#define SEC_GRP1COND11 (LIFEC_SEC_BASE + 0x01B4U)
#define SEC_GRP0COND12 (LIFEC_SEC_BASE + 0x01B8U)
#define SEC_GRP1COND12 (LIFEC_SEC_BASE + 0x01BCU)
#define SEC_GRP0COND13 (LIFEC_SEC_BASE + 0x01C0U)
#define SEC_GRP1COND13 (LIFEC_SEC_BASE + 0x01C4U)
#define SEC_GRP0COND14 (LIFEC_SEC_BASE + 0x01C8U)
#define SEC_GRP1COND14 (LIFEC_SEC_BASE + 0x01CCU)
#define SEC_GRP0COND15 (LIFEC_SEC_BASE + 0x01D0U)
#define SEC_GRP1COND15 (LIFEC_SEC_BASE + 0x01D4U)
#define SEC_READONLY0 (LIFEC_SEC_BASE + 0x01D8U)
#define SEC_READONLY1 (LIFEC_SEC_BASE + 0x01DCU)
#define SEC_READONLY2 (LIFEC_SEC_BASE + 0x01E0U)
#define SEC_READONLY3 (LIFEC_SEC_BASE + 0x01E4U)
#define SEC_READONLY4 (LIFEC_SEC_BASE + 0x01E8U)
#define SEC_READONLY5 (LIFEC_SEC_BASE + 0x01ECU)
#define SEC_READONLY6 (LIFEC_SEC_BASE + 0x01F0U)
#define SEC_READONLY7 (LIFEC_SEC_BASE + 0x01F4U)
#define SEC_READONLY8 (LIFEC_SEC_BASE + 0x01F8U)
#define SEC_READONLY9 (LIFEC_SEC_BASE + 0x01FCU)
#define SEC_READONLY10 (LIFEC_SEC_BASE + 0x0200U)
#define SEC_READONLY11 (LIFEC_SEC_BASE + 0x0204U)
#define SEC_READONLY12 (LIFEC_SEC_BASE + 0x0208U)
#define SEC_READONLY13 (LIFEC_SEC_BASE + 0x020CU)
#define SEC_READONLY14 (LIFEC_SEC_BASE + 0x0210U)
#define SEC_READONLY15 (LIFEC_SEC_BASE + 0x0214U)
#define LIFEC_SAFE_BASE (0xE6120000U)
#define SAFE_GRP0CR0 (LIFEC_SAFE_BASE + 0x0138U)
#define SAFE_GRP1CR0 (LIFEC_SAFE_BASE + 0x013CU)
#define SAFE_GRP0CR1 (LIFEC_SAFE_BASE + 0x0140U)
#define SAFE_GRP1CR1 (LIFEC_SAFE_BASE + 0x0144U)
#define SAFE_GRP0CR2 (LIFEC_SAFE_BASE + 0x0148U)
#define SAFE_GRP1CR2 (LIFEC_SAFE_BASE + 0x014CU)
#define SAFE_GRP0CR3 (LIFEC_SAFE_BASE + 0x0150U)
#define SAFE_GRP1CR3 (LIFEC_SAFE_BASE + 0x0154U)
#define SAFE_GRP0COND0 (LIFEC_SAFE_BASE + 0x0158U)
#define SAFE_GRP1COND0 (LIFEC_SAFE_BASE + 0x015CU)
#define SAFE_GRP0COND1 (LIFEC_SAFE_BASE + 0x0160U)
#define SAFE_GRP1COND1 (LIFEC_SAFE_BASE + 0x0164U)
#define SAFE_GRP0COND2 (LIFEC_SAFE_BASE + 0x0168U)
#define SAFE_GRP1COND2 (LIFEC_SAFE_BASE + 0x016CU)
#define SAFE_GRP0COND3 (LIFEC_SAFE_BASE + 0x0170U)
#define SAFE_GRP1COND3 (LIFEC_SAFE_BASE + 0x0174U)
#define SAFE_GRP0COND4 (LIFEC_SAFE_BASE + 0x0178U)
#define SAFE_GRP1COND4 (LIFEC_SAFE_BASE + 0x017CU)
#define SAFE_GRP0COND5 (LIFEC_SAFE_BASE + 0x0180U)
#define SAFE_GRP1COND5 (LIFEC_SAFE_BASE + 0x0184U)
#define SAFE_GRP0COND6 (LIFEC_SAFE_BASE + 0x0188U)
#define SAFE_GRP1COND6 (LIFEC_SAFE_BASE + 0x018CU)
#define SAFE_GRP0COND7 (LIFEC_SAFE_BASE + 0x0190U)
#define SAFE_GRP1COND7 (LIFEC_SAFE_BASE + 0x0194U)
#define SAFE_GRP0COND8 (LIFEC_SAFE_BASE + 0x0198U)
#define SAFE_GRP1COND8 (LIFEC_SAFE_BASE + 0x019CU)
#define SAFE_GRP0COND9 (LIFEC_SAFE_BASE + 0x01A0U)
#define SAFE_GRP1COND9 (LIFEC_SAFE_BASE + 0x01A4U)
#define SAFE_GRP0COND10 (LIFEC_SAFE_BASE + 0x01A8U)
#define SAFE_GRP1COND10 (LIFEC_SAFE_BASE + 0x01ACU)
#define SAFE_GRP0COND11 (LIFEC_SAFE_BASE + 0x01B0U)
#define SAFE_GRP1COND11 (LIFEC_SAFE_BASE + 0x01B4U)
#define SAFE_GRP0COND12 (LIFEC_SAFE_BASE + 0x01B8U)
#define SAFE_GRP1COND12 (LIFEC_SAFE_BASE + 0x01BCU)
#define SAFE_GRP0COND13 (LIFEC_SAFE_BASE + 0x01C0U)
#define SAFE_GRP1COND13 (LIFEC_SAFE_BASE + 0x01C4U)
#define SAFE_GRP0COND14 (LIFEC_SAFE_BASE + 0x01C8U)
#define SAFE_GRP1COND14 (LIFEC_SAFE_BASE + 0x01CCU)
#define SAFE_GRP0COND15 (LIFEC_SAFE_BASE + 0x01D0U)
#define SAFE_GRP1COND15 (LIFEC_SAFE_BASE + 0x01D4U)
#define SAFE_READONLY0 (LIFEC_SAFE_BASE + 0x01D8U)
#define SAFE_READONLY1 (LIFEC_SAFE_BASE + 0x01DCU)
#define SAFE_READONLY2 (LIFEC_SAFE_BASE + 0x01E0U)
#define SAFE_READONLY3 (LIFEC_SAFE_BASE + 0x01E4U)
#define SAFE_READONLY4 (LIFEC_SAFE_BASE + 0x01E8U)
#define SAFE_READONLY5 (LIFEC_SAFE_BASE + 0x01ECU)
#define SAFE_READONLY6 (LIFEC_SAFE_BASE + 0x01F0U)
#define SAFE_READONLY7 (LIFEC_SAFE_BASE + 0x01F4U)
#define SAFE_READONLY8 (LIFEC_SAFE_BASE + 0x01F8U)
#define SAFE_READONLY9 (LIFEC_SAFE_BASE + 0x01FCU)
#define SAFE_READONLY10 (LIFEC_SAFE_BASE + 0x0200U)
#define SAFE_READONLY11 (LIFEC_SAFE_BASE + 0x0204U)
#define SAFE_READONLY12 (LIFEC_SAFE_BASE + 0x0208U)
#define SAFE_READONLY13 (LIFEC_SAFE_BASE + 0x020CU)
#define SAFE_READONLY14 (LIFEC_SAFE_BASE + 0x0210U)
#define SAFE_READONLY15 (LIFEC_SAFE_BASE + 0x0214U)
Standardise header guards across codebase All identifiers, regardless of use, that start with two underscores are reserved. This means they can't be used in header guards. The style that this project is now to use the full name of the file in capital letters followed by 'H'. For example, for a file called "uart_example.h", the header guard is UART_EXAMPLE_H. The exceptions are files that are imported from other projects: - CryptoCell driver - dt-bindings folders - zlib headers Change-Id: I50561bf6c88b491ec440d0c8385c74650f3c106e Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-11-08 10:20:19 +00:00
#endif /* LIFEC_REGISTERS_H */