2019-10-22 03:31:45 +01:00
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/*
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2020-05-14 07:53:29 +01:00
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* Copyright (c) 2019-2020, Intel Corporation. All rights reserved.
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2019-10-22 03:31:45 +01:00
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef SOCFPGA_SIP_SVC_H
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#define SOCFPGA_SIP_SVC_H
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/* SiP status response */
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#define INTEL_SIP_SMC_STATUS_OK 0
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#define INTEL_SIP_SMC_STATUS_BUSY 0x1
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#define INTEL_SIP_SMC_STATUS_REJECTED 0x2
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2020-02-27 02:23:48 +00:00
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#define INTEL_SIP_SMC_STATUS_ERROR 0x4
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#define INTEL_SIP_SMC_RSU_ERROR 0x7
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2019-10-22 03:31:45 +01:00
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/* SMC SiP service function identifier */
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2020-05-14 07:53:29 +01:00
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/* FPGA Reconfig */
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2019-10-22 03:31:45 +01:00
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#define INTEL_SIP_SMC_FPGA_CONFIG_START 0xC2000001
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#define INTEL_SIP_SMC_FPGA_CONFIG_WRITE 0x42000002
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#define INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE 0xC2000003
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#define INTEL_SIP_SMC_FPGA_CONFIG_ISDONE 0xC2000004
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#define INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM 0xC2000005
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2020-05-14 07:53:29 +01:00
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/* Secure Register Access */
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2019-10-22 03:31:45 +01:00
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#define INTEL_SIP_SMC_REG_READ 0xC2000007
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#define INTEL_SIP_SMC_REG_WRITE 0xC2000008
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#define INTEL_SIP_SMC_REG_UPDATE 0xC2000009
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2020-05-14 07:53:29 +01:00
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/* Remote System Update */
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2019-10-22 03:31:45 +01:00
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#define INTEL_SIP_SMC_RSU_STATUS 0xC200000B
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#define INTEL_SIP_SMC_RSU_UPDATE 0xC200000C
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#define INTEL_SIP_SMC_RSU_NOTIFY 0xC200000E
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#define INTEL_SIP_SMC_RSU_RETRY_COUNTER 0xC200000F
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2020-05-14 07:53:29 +01:00
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/* Send Mailbox Command */
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2019-12-17 11:30:41 +00:00
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#define INTEL_SIP_SMC_MBOX_SEND_CMD 0xC200001E
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2019-10-22 03:31:45 +01:00
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2020-05-14 07:53:29 +01:00
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/* SiP Definitions */
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2019-10-22 03:31:45 +01:00
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/* FPGA config helpers */
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2019-10-30 06:49:40 +00:00
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#define INTEL_SIP_SMC_FPGA_CONFIG_ADDR 0x400000
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2020-04-13 15:40:43 +01:00
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#define INTEL_SIP_SMC_FPGA_CONFIG_SIZE 0x2000000
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2019-10-22 03:31:45 +01:00
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/* SMC function IDs for SiP Service queries */
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#define SIP_SVC_CALL_COUNT 0x8200ff00
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#define SIP_SVC_UID 0x8200ff01
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#define SIP_SVC_VERSION 0x8200ff03
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/* SiP Service Calls version numbers */
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#define SIP_SVC_VERSION_MAJOR 0
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#define SIP_SVC_VERSION_MINOR 1
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2020-05-18 04:16:48 +01:00
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/* Structure Definitions */
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struct fpga_config_info {
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uint32_t addr;
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int size;
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int size_written;
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uint32_t write_requested;
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int subblocks_sent;
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int block_number;
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};
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/* Function Definitions */
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bool is_address_in_ddr_range(uint64_t addr, uint64_t size);
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2019-10-22 03:31:45 +01:00
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#endif /* SOCFPGA_SIP_SVC_H */
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