2020-10-23 13:22:07 +01:00
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/*
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2022-01-18 07:59:06 +00:00
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* Copyright (c) 2020-2022, Arm Limited. All rights reserved.
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2020-10-23 13:22:07 +01:00
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef NEOVERSE_N2_H
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#define NEOVERSE_N2_H
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/* Neoverse N2 ID register for revision r0p0 */
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2021-09-28 17:46:45 +01:00
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#define NEOVERSE_N2_MIDR U(0x410FD490)
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2020-10-23 13:22:07 +01:00
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2022-01-18 07:59:06 +00:00
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/* Neoverse N2 loop count for CVE-2022-23960 mitigation */
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#define NEOVERSE_N2_BHB_LOOP_COUNT U(32)
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2020-10-23 13:22:07 +01:00
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/*******************************************************************************
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* CPU Power control register
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******************************************************************************/
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2021-09-28 17:46:45 +01:00
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#define NEOVERSE_N2_CPUPWRCTLR_EL1 S3_0_C15_C2_7
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#define NEOVERSE_N2_CORE_PWRDN_EN_BIT (ULL(1) << 0)
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2020-10-23 13:22:07 +01:00
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/*******************************************************************************
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* CPU Extended Control register specific definitions.
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******************************************************************************/
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2021-09-28 17:46:45 +01:00
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#define NEOVERSE_N2_CPUECTLR_EL1 S3_0_C15_C1_4
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#define NEOVERSE_N2_CPUECTLR_EL1_EXTLLC_BIT (ULL(1) << 0)
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#define NEOVERSE_N2_CPUECTLR_EL1_PFSTIDIS_BIT (ULL(1) << 8)
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2020-10-23 13:22:07 +01:00
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/*******************************************************************************
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* CPU Auxiliary Control register specific definitions.
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******************************************************************************/
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2021-09-28 17:46:45 +01:00
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#define NEOVERSE_N2_CPUACTLR_EL1 S3_0_C15_C1_0
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#define NEOVERSE_N2_CPUACTLR_EL1_BIT_46 (ULL(1) << 46)
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2021-10-06 23:31:24 +01:00
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#define NEOVERSE_N2_CPUACTLR_EL1_BIT_22 (ULL(1) << 22)
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2021-03-30 22:08:32 +01:00
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/*******************************************************************************
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* CPU Auxiliary Control register 2 specific definitions.
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******************************************************************************/
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2021-09-28 17:46:45 +01:00
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#define NEOVERSE_N2_CPUACTLR2_EL1 S3_0_C15_C1_1
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#define NEOVERSE_N2_CPUACTLR2_EL1_BIT_2 (ULL(1) << 2)
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2020-10-23 13:22:07 +01:00
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2021-08-30 19:02:51 +01:00
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/*******************************************************************************
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* CPU Auxiliary Control register 5 specific definitions.
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******************************************************************************/
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2021-09-28 17:46:45 +01:00
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#define NEOVERSE_N2_CPUACTLR5_EL1 S3_0_C15_C8_0
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#define NEOVERSE_N2_CPUACTLR5_EL1_BIT_44 (ULL(1) << 44)
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2021-10-21 02:28:58 +01:00
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#define NEOVERSE_N2_CPUACTLR5_EL1_BIT_13 (ULL(1) << 13)
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2021-10-08 01:59:33 +01:00
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#define NEOVERSE_N2_CPUACTLR5_EL1_BIT_17 (ULL(1) << 17)
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2021-09-28 17:46:45 +01:00
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/*******************************************************************************
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* CPU Auxiliary Control register specific definitions.
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******************************************************************************/
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#define NEOVERSE_N2_CPUECTLR2_EL1 S3_0_C15_C1_5
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#define NEOVERSE_N2_CPUECTLR2_EL1_PF_MODE_CNSRV ULL(9)
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#define CPUECTLR2_EL1_PF_MODE_LSB U(11)
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#define CPUECTLR2_EL1_PF_MODE_WIDTH U(4)
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2021-08-30 19:02:51 +01:00
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2020-10-23 13:22:07 +01:00
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#endif /* NEOVERSE_N2_H */
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