2021-05-05 00:14:09 +01:00
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/*
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* Copyright (c) 2021, NVIDIA Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <errno.h>
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#include <arch.h>
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#include <arch_helpers.h>
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#include <drivers/arm/gic600ae_fmu.h>
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#include <drivers/delay_timer.h>
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#include <lib/mmio.h>
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#define GICFMU_IDLE_TIMEOUT_US U(2000000)
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/* Macro to write 32-bit FMU registers */
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#define GIC_FMU_WRITE_32(base, reg, val) \
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do { \
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/* \
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* This register receives the unlock key that is required for \
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* writes to FMU registers to be successful. \
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*/ \
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mmio_write_32(base + GICFMU_KEY, 0xBE); \
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/* Perform the actual write */ \
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mmio_write_32((base) + (reg), (val)); \
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} while (false)
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/* Macro to write 64-bit FMU registers */
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#define GIC_FMU_WRITE_64(base, reg, n, val) \
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do { \
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/* \
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* This register receives the unlock key that is required for \
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* writes to FMU registers to be successful. \
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*/ \
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mmio_write_32(base + GICFMU_KEY, 0xBE); \
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/* \
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* APB bus is 32-bit wide; so split the 64-bit write into \
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* two 32-bit writes \
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*/ \
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mmio_write_32((base) + reg##_LO + (n * 64), (val)); \
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mmio_write_32((base) + reg##_HI + (n * 64), (val)); \
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} while (false)
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/* Helper function to wait until FMU is ready to accept the next command */
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static void wait_until_fmu_is_idle(uintptr_t base)
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{
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2021-11-18 11:18:13 +00:00
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uint32_t timeout_count = GICFMU_IDLE_TIMEOUT_US;
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2021-05-05 00:14:09 +01:00
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uint64_t status;
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/* wait until status is 'busy' */
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do {
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status = (gic_fmu_read_status(base) & BIT(0));
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2021-11-18 11:18:13 +00:00
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if (timeout_count-- == 0U) {
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2021-05-05 00:14:09 +01:00
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ERROR("GIC600 AE FMU is not responding\n");
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panic();
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}
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2021-11-18 11:18:13 +00:00
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udelay(1U);
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2021-05-05 00:14:09 +01:00
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} while (status == U(0));
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}
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#define GIC_FMU_WRITE_ON_IDLE_32(base, reg, val) \
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do { \
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/* Wait until FMU is ready */ \
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wait_until_fmu_is_idle(base); \
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/* Actual register write */ \
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GIC_FMU_WRITE_32(base, reg, val); \
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/* Wait until FMU is ready */ \
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wait_until_fmu_is_idle(base); \
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} while (false)
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#define GIC_FMU_WRITE_ON_IDLE_64(base, reg, n, val) \
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do { \
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/* Wait until FMU is ready */ \
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wait_until_fmu_is_idle(base); \
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/* Actual register write */ \
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GIC_FMU_WRITE_64(base, reg, n, val); \
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/* Wait until FMU is ready */ \
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wait_until_fmu_is_idle(base); \
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} while (false)
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/*******************************************************************************
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* GIC FMU functions for accessing the Fault Management Unit registers
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******************************************************************************/
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/*
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* Accessors to read the Error Record Feature Register bits corresponding
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* to an error record 'n'
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*/
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uint64_t gic_fmu_read_errfr(uintptr_t base, unsigned int n)
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{
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/*
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* APB bus is 32-bit wide; so split the 64-bit read into
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* two 32-bit reads
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*/
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uint64_t reg_val = (uint64_t)mmio_read_32(base + GICFMU_ERRFR_LO + n * 64U);
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reg_val |= ((uint64_t)mmio_read_32(base + GICFMU_ERRFR_HI + n * 64U) << 32);
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return reg_val;
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}
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/*
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* Accessors to read the Error Record Control Register bits corresponding
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* to an error record 'n'
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*/
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uint64_t gic_fmu_read_errctlr(uintptr_t base, unsigned int n)
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{
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/*
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* APB bus is 32-bit wide; so split the 64-bit read into
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* two 32-bit reads
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*/
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uint64_t reg_val = (uint64_t)mmio_read_32(base + GICFMU_ERRCTLR_LO + n * 64U);
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reg_val |= ((uint64_t)mmio_read_32(base + GICFMU_ERRCTLR_HI + n * 64U) << 32);
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return reg_val;
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}
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/*
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* Accessors to read the Error Record Primary Status Register bits
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* corresponding to an error record 'n'
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*/
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uint64_t gic_fmu_read_errstatus(uintptr_t base, unsigned int n)
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{
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/*
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* APB bus is 32-bit wide; so split the 64-bit read into
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* two 32-bit reads
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*/
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uint64_t reg_val = (uint64_t)mmio_read_32(base + GICFMU_ERRSTATUS_LO + n * 64U);
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reg_val |= ((uint64_t)mmio_read_32(base + GICFMU_ERRSTATUS_HI + n * 64U) << 32);
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return reg_val;
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}
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/*
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* Accessors to read the Error Group Status Register
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*/
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uint64_t gic_fmu_read_errgsr(uintptr_t base)
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{
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/*
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* APB bus is 32-bit wide; so split the 64-bit read into
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* two 32-bit reads
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*/
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uint64_t reg_val = (uint64_t)mmio_read_32(base + GICFMU_ERRGSR_LO);
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reg_val |= ((uint64_t)mmio_read_32(base + GICFMU_ERRGSR_HI) << 32);
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return reg_val;
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}
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/*
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* Accessors to read the Ping Control Register
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*/
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uint32_t gic_fmu_read_pingctlr(uintptr_t base)
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{
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return mmio_read_32(base + GICFMU_PINGCTLR);
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}
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/*
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* Accessors to read the Ping Now Register
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*/
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uint32_t gic_fmu_read_pingnow(uintptr_t base)
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{
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return mmio_read_32(base + GICFMU_PINGNOW);
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}
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/*
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* Accessors to read the Ping Mask Register
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*/
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uint64_t gic_fmu_read_pingmask(uintptr_t base)
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{
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/*
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* APB bus is 32-bit wide; so split the 64-bit read into
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* two 32-bit reads
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*/
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uint64_t reg_val = (uint64_t)mmio_read_32(base + GICFMU_PINGMASK_LO);
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reg_val |= ((uint64_t)mmio_read_32(base + GICFMU_PINGMASK_HI) << 32);
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return reg_val;
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}
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/*
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* Accessors to read the FMU Status Register
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*/
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uint32_t gic_fmu_read_status(uintptr_t base)
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{
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return mmio_read_32(base + GICFMU_STATUS);
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}
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/*
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* Accessors to read the Error Record ID Register
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*/
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uint32_t gic_fmu_read_erridr(uintptr_t base)
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{
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return mmio_read_32(base + GICFMU_ERRIDR);
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}
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/*
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* Accessors to write a 64 bit value to the Error Record Control Register
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*/
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void gic_fmu_write_errctlr(uintptr_t base, unsigned int n, uint64_t val)
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{
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GIC_FMU_WRITE_64(base, GICFMU_ERRCTLR, n, val);
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}
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/*
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* Accessors to write a 64 bit value to the Error Record Primary Status
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* Register
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*/
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void gic_fmu_write_errstatus(uintptr_t base, unsigned int n, uint64_t val)
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{
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/* Wait until FMU is ready before writing */
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GIC_FMU_WRITE_ON_IDLE_64(base, GICFMU_ERRSTATUS, n, val);
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}
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/*
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* Accessors to write a 32 bit value to the Ping Control Register
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*/
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void gic_fmu_write_pingctlr(uintptr_t base, uint32_t val)
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{
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GIC_FMU_WRITE_32(base, GICFMU_PINGCTLR, val);
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}
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/*
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* Accessors to write a 32 bit value to the Ping Now Register
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*/
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void gic_fmu_write_pingnow(uintptr_t base, uint32_t val)
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{
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/* Wait until FMU is ready before writing */
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GIC_FMU_WRITE_ON_IDLE_32(base, GICFMU_PINGNOW, val);
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}
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/*
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* Accessors to write a 32 bit value to the Safety Mechanism Enable Register
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*/
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void gic_fmu_write_smen(uintptr_t base, uint32_t val)
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{
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/* Wait until FMU is ready before writing */
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GIC_FMU_WRITE_ON_IDLE_32(base, GICFMU_SMEN, val);
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}
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/*
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* Accessors to write a 32 bit value to the Safety Mechanism Inject Error
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* Register
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*/
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void gic_fmu_write_sminjerr(uintptr_t base, uint32_t val)
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{
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/* Wait until FMU is ready before writing */
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GIC_FMU_WRITE_ON_IDLE_32(base, GICFMU_SMINJERR, val);
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}
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/*
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* Accessors to write a 64 bit value to the Ping Mask Register
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*/
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void gic_fmu_write_pingmask(uintptr_t base, uint64_t val)
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{
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GIC_FMU_WRITE_64(base, GICFMU_PINGMASK, 0, val);
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}
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