128 lines
4.4 KiB
C
128 lines
4.4 KiB
C
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/*
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* Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __PLAT_PRIVATE_H__
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#define __PLAT_PRIVATE_H__
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#ifndef __ASSEMBLY__
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#include <mmio.h>
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#include <stdint.h>
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#include <xlat_tables.h>
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/******************************************************************************
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* For rockchip socs pm ops
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******************************************************************************/
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struct rockchip_pm_ops_cb {
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int (*cores_pwr_dm_on)(unsigned long mpidr, uint64_t entrypoint);
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int (*cores_pwr_dm_off)(void);
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int (*cores_pwr_dm_on_finish)(void);
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int (*cores_pwr_dm_suspend)(void);
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int (*cores_pwr_dm_resume)(void);
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int (*sys_pwr_dm_suspend)(void);
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int (*sys_pwr_dm_resume)(void);
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void (*sys_gbl_soft_reset)(void) __dead2;
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void (*system_off)(void) __dead2;
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};
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/******************************************************************************
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* The register have write-mask bits, it is mean, if you want to set the bits,
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* you needs set the write-mask bits at the same time,
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* The write-mask bits is in high 16-bits.
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* The fllowing macro definition helps access write-mask bits reg efficient!
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******************************************************************************/
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#define REG_MSK_SHIFT 16
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#ifndef BIT
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#define BIT(nr) (1 << (nr))
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#endif
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#ifndef WMSK_BIT
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#define WMSK_BIT(nr) BIT((nr) + REG_MSK_SHIFT)
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#endif
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/* set one bit with write mask */
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#ifndef BIT_WITH_WMSK
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#define BIT_WITH_WMSK(nr) (BIT(nr) | WMSK_BIT(nr))
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#endif
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#ifndef BITS_SHIFT
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#define BITS_SHIFT(bits, shift) (bits << (shift))
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#endif
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#ifndef BITS_WITH_WMASK
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#define BITS_WITH_WMASK(msk, bits, shift)\
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(BITS_SHIFT(bits, shift) | BITS_SHIFT(msk, (shift + REG_MSK_SHIFT)))
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#endif
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/******************************************************************************
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* Function and variable prototypes
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*****************************************************************************/
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void plat_configure_mmu_el3(unsigned long total_base,
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unsigned long total_size,
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unsigned long,
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unsigned long,
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unsigned long,
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unsigned long);
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void plat_cci_init(void);
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void plat_cci_enable(void);
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void plat_cci_disable(void);
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void plat_delay_timer_init(void);
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void plat_rockchip_gic_driver_init(void);
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void plat_rockchip_gic_init(void);
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void plat_rockchip_gic_cpuif_enable(void);
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void plat_rockchip_gic_cpuif_disable(void);
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void plat_rockchip_gic_pcpu_init(void);
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void plat_rockchip_pmusram_prepare(void);
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void plat_rockchip_pmu_init(void);
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void plat_rockchip_soc_init(void);
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void plat_setup_rockchip_pm_ops(struct rockchip_pm_ops_cb *ops);
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extern const unsigned char rockchip_power_domain_tree_desc[];
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extern void *pmu_cpuson_entrypoint_start;
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extern void *pmu_cpuson_entrypoint_end;
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extern uint64_t cpuson_entry_point[PLATFORM_CORE_COUNT];
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extern uint32_t cpuson_flags[PLATFORM_CORE_COUNT];
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extern const mmap_region_t plat_rk_mmap[];
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#endif /* __ASSEMBLY__ */
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/* only Cortex-A53 */
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#define RK_PLAT_CFG0 0
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/* include Cortex-A72 */
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#define RK_PLAT_CFG1 1
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#endif /* __PLAT_PRIVATE_H__ */
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