2015-08-25 12:33:14 +01:00
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/*
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* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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2015-09-14 05:01:39 +01:00
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#include <arch.h>
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#include <arch_helpers.h>
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2016-01-05 23:17:41 +00:00
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#include <assert.h>
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#include <bl_common.h>
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#include <context.h>
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#include <context_mgmt.h>
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2015-09-14 05:01:39 +01:00
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#include <debug.h>
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#include <mce.h>
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2015-08-25 12:33:14 +01:00
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#include <psci.h>
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2017-03-14 21:25:35 +00:00
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#include <t18x_ari.h>
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2015-08-25 12:33:14 +01:00
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#include <tegra_private.h>
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int32_t tegra_soc_validate_power_state(unsigned int power_state)
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{
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/* Sanity check the requested afflvl */
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if (psci_get_pstate_type(power_state) == PSTATE_TYPE_STANDBY) {
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/*
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* It's possible to enter standby only on affinity level 0 i.e.
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* a cpu on Tegra. Ignore any other affinity level.
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*/
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if (psci_get_pstate_afflvl(power_state) != MPIDR_AFFLVL0)
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return PSCI_E_INVALID_PARAMS;
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}
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return PSCI_E_SUCCESS;
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}
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2015-09-14 05:01:39 +01:00
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int tegra_soc_prepare_cpu_on(unsigned long mpidr)
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{
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int target_cpu = mpidr & MPIDR_CPU_MASK;
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int target_cluster = (mpidr & MPIDR_CLUSTER_MASK) >>
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MPIDR_AFFINITY_BITS;
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if (target_cluster > MPIDR_AFFLVL1) {
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ERROR("%s: unsupported CPU (0x%lx)\n", __func__, mpidr);
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return PSCI_E_NOT_PRESENT;
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}
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/* construct the target CPU # */
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target_cpu |= (target_cluster << 2);
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mce_command_handler(MCE_CMD_ONLINE_CORE, target_cpu, 0, 0);
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return PSCI_E_SUCCESS;
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}
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int tegra_soc_prepare_cpu_on_finish(unsigned long mpidr)
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{
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/*
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* Check if we are exiting from SOC_POWERDN.
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*/
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if (tegra_system_suspended()) {
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/*
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* System resume complete.
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*/
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tegra_pm_system_suspend_exit();
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}
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return PSCI_E_SUCCESS;
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}
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int tegra_soc_prepare_cpu_off(unsigned long mpidr)
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{
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2016-01-05 23:17:41 +00:00
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cpu_context_t *ctx = cm_get_context(NON_SECURE);
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gp_regs_t *gp_regs = get_gpregs_ctx(ctx);
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assert(ctx);
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assert(gp_regs);
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2015-09-14 05:01:39 +01:00
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/* Turn off wake_mask */
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2016-01-05 23:17:41 +00:00
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write_ctx_reg(gp_regs, CTX_GPREG_X4, 0);
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write_ctx_reg(gp_regs, CTX_GPREG_X5, 0);
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write_ctx_reg(gp_regs, CTX_GPREG_X6, 1);
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mce_command_handler(MCE_CMD_UPDATE_CSTATE_INFO, TEGRA_ARI_CLUSTER_CC7,
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0, TEGRA_ARI_SYSTEM_SC7);
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2015-09-14 05:01:39 +01:00
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/* Turn off CPU */
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2016-01-05 23:17:41 +00:00
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return mce_command_handler(MCE_CMD_ENTER_CSTATE, TEGRA_ARI_CORE_C7,
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~0, 0);
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2015-09-14 05:01:39 +01:00
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}
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2017-03-14 21:25:35 +00:00
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__dead2 void tegra_soc_prepare_system_off(void)
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{
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mce_enter_ccplex_state(TEGRA_ARI_MISC_CCPLEX_SHUTDOWN_POWER_OFF);
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}
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