2019-12-09 20:02:22 +00:00
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/*
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2021-05-18 21:23:31 +01:00
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* Copyright (c) 2021, Arm Limited. All rights reserved.
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2019-12-09 20:02:22 +00:00
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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2021-05-18 21:23:31 +01:00
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#ifndef CORTEX_X2_H
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#define CORTEX_X2_H
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2019-12-09 20:02:22 +00:00
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2021-05-18 21:23:31 +01:00
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#define CORTEX_X2_MIDR U(0x410FD480)
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2019-12-09 20:02:22 +00:00
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/*******************************************************************************
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* CPU Extended Control register specific definitions
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******************************************************************************/
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2021-05-18 21:23:31 +01:00
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#define CORTEX_X2_CPUECTLR_EL1 S3_0_C15_C1_4
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2019-12-09 20:02:22 +00:00
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/*******************************************************************************
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* CPU Power Control register specific definitions
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******************************************************************************/
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2021-05-18 21:23:31 +01:00
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#define CORTEX_X2_CPUPWRCTLR_EL1 S3_0_C15_C2_7
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#define CORTEX_X2_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
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2019-12-09 20:02:22 +00:00
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2021-12-01 23:40:39 +00:00
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/*******************************************************************************
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* CPU Auxiliary Control Register 5 definitions
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******************************************************************************/
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#define CORTEX_X2_CPUACTLR5_EL1 S3_0_C15_C8_0
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2021-05-18 21:23:31 +01:00
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#endif /* CORTEX_X2_H */
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