2019-12-08 07:14:03 +00:00
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/*
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* Copyright (c) 2017-2020, STMicroelectronics - All Rights Reserved
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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2020-05-13 09:13:54 +01:00
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#include <assert.h>
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#include <stdint.h>
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#include <platform_def.h>
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#include <common/debug.h>
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2020-05-13 09:07:45 +01:00
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#include <drivers/st/etzpc.h>
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2020-05-13 09:13:54 +01:00
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#include <drivers/st/stm32_gpio.h>
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2019-12-08 07:14:03 +00:00
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#include <stm32mp_shared_resources.h>
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2020-05-13 09:07:45 +01:00
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/*
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* Once one starts to get the resource registering state, one cannot register
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* new resources. This ensures resource state cannot change.
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*/
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static bool registering_locked;
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/*
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* Shared peripherals and resources registration
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*
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* Each resource assignation is stored in a table. The state defaults
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* to PERIPH_UNREGISTERED if the resource is not explicitly assigned.
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*
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* Resource driver that as not embedded (a.k.a their related CFG_xxx build
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* directive is disabled) are assigned to the non-secure world.
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*
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* Each pin of the GPIOZ bank can be secure or non-secure.
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*
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* It is the platform responsibility the ensure resource assignation
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* matches the access permission firewalls configuration.
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*/
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enum shres_state {
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SHRES_UNREGISTERED = 0,
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SHRES_SECURE,
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SHRES_NON_SECURE,
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};
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/* Force uint8_t array for array of enum shres_state for size considerations */
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static uint8_t shres_state[STM32MP1_SHRES_COUNT];
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2020-05-13 14:51:56 +01:00
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static const char *shres2str_id_tbl[STM32MP1_SHRES_COUNT] __unused = {
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[STM32MP1_SHRES_GPIOZ(0)] = "GPIOZ0",
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[STM32MP1_SHRES_GPIOZ(1)] = "GPIOZ1",
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[STM32MP1_SHRES_GPIOZ(2)] = "GPIOZ2",
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[STM32MP1_SHRES_GPIOZ(3)] = "GPIOZ3",
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[STM32MP1_SHRES_GPIOZ(4)] = "GPIOZ4",
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[STM32MP1_SHRES_GPIOZ(5)] = "GPIOZ5",
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[STM32MP1_SHRES_GPIOZ(6)] = "GPIOZ6",
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[STM32MP1_SHRES_GPIOZ(7)] = "GPIOZ7",
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[STM32MP1_SHRES_IWDG1] = "IWDG1",
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[STM32MP1_SHRES_USART1] = "USART1",
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[STM32MP1_SHRES_SPI6] = "SPI6",
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[STM32MP1_SHRES_I2C4] = "I2C4",
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[STM32MP1_SHRES_RNG1] = "RNG1",
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[STM32MP1_SHRES_HASH1] = "HASH1",
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[STM32MP1_SHRES_CRYP1] = "CRYP1",
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[STM32MP1_SHRES_I2C6] = "I2C6",
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[STM32MP1_SHRES_RTC] = "RTC",
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[STM32MP1_SHRES_MCU] = "MCU",
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[STM32MP1_SHRES_MDMA] = "MDMA",
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[STM32MP1_SHRES_PLL3] = "PLL3",
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};
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static const char __unused *shres2str_id(enum stm32mp_shres id)
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{
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assert(id < ARRAY_SIZE(shres2str_id_tbl));
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return shres2str_id_tbl[id];
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}
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static const char __unused *shres2str_state_tbl[] = {
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[SHRES_UNREGISTERED] = "unregistered",
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[SHRES_NON_SECURE] = "non-secure",
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[SHRES_SECURE] = "secure",
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};
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static const char __unused *shres2str_state(unsigned int state)
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{
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assert(state < ARRAY_SIZE(shres2str_state_tbl));
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return shres2str_state_tbl[state];
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}
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2020-05-13 09:07:45 +01:00
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/* Get resource state: these accesses lock the registering support */
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static void lock_registering(void)
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{
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registering_locked = true;
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}
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static bool periph_is_non_secure(enum stm32mp_shres id)
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{
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lock_registering();
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return (shres_state[id] == SHRES_NON_SECURE) ||
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(shres_state[id] == SHRES_UNREGISTERED);
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}
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static bool periph_is_secure(enum stm32mp_shres id)
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{
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return !periph_is_non_secure(id);
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}
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2020-05-13 09:13:54 +01:00
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/* GPIOZ pin count is saved in RAM to prevent parsing FDT several times */
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static int8_t gpioz_nbpin = -1;
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static unsigned int get_gpio_nbpin(unsigned int bank)
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{
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if (bank != GPIO_BANK_Z) {
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int count = fdt_get_gpio_bank_pin_count(bank);
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assert((count >= 0) || (count <= (GPIO_PIN_MAX + 1)));
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return (unsigned int)count;
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}
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if (gpioz_nbpin < 0) {
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int count = fdt_get_gpio_bank_pin_count(GPIO_BANK_Z);
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assert((count == 0) || (count == STM32MP_GPIOZ_PIN_MAX_COUNT));
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gpioz_nbpin = count;
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}
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return (unsigned int)gpioz_nbpin;
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}
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2020-05-13 09:07:45 +01:00
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static unsigned int get_gpioz_nbpin(void)
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2020-05-13 09:13:54 +01:00
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{
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return get_gpio_nbpin(GPIO_BANK_Z);
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}
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2019-12-08 07:14:03 +00:00
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/* Currently allow full access by non-secure to platform clock services */
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bool stm32mp_nsec_can_access_clock(unsigned long clock_id)
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{
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return true;
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}
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/* Currently allow full access by non-secure to platform reset services */
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bool stm32mp_nsec_can_access_reset(unsigned int reset_id)
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{
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return true;
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}
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2020-05-13 09:07:45 +01:00
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static bool mckprot_protects_periph(enum stm32mp_shres id)
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{
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switch (id) {
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case STM32MP1_SHRES_MCU:
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case STM32MP1_SHRES_PLL3:
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return true;
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default:
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return false;
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}
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}
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/* ETZPC configuration at drivers initialization completion */
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static enum etzpc_decprot_attributes shres2decprot_attr(enum stm32mp_shres id)
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{
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assert((id < STM32MP1_SHRES_GPIOZ(0)) ||
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(id > STM32MP1_SHRES_GPIOZ(7)));
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if (periph_is_non_secure(id)) {
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return ETZPC_DECPROT_NS_RW;
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}
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return ETZPC_DECPROT_S_RW;
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}
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static void set_etzpc_secure_configuration(void)
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{
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/* Some system peripherals shall be secure */
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etzpc_configure_decprot(STM32MP1_ETZPC_STGENC_ID, ETZPC_DECPROT_S_RW);
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etzpc_configure_decprot(STM32MP1_ETZPC_BKPSRAM_ID, ETZPC_DECPROT_S_RW);
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etzpc_configure_decprot(STM32MP1_ETZPC_DDRCTRL_ID,
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ETZPC_DECPROT_NS_R_S_W);
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etzpc_configure_decprot(STM32MP1_ETZPC_DDRPHYC_ID,
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ETZPC_DECPROT_NS_R_S_W);
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/* Configure ETZPC with peripheral registering */
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etzpc_configure_decprot(STM32MP1_ETZPC_CRYP1_ID,
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shres2decprot_attr(STM32MP1_SHRES_CRYP1));
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etzpc_configure_decprot(STM32MP1_ETZPC_HASH1_ID,
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shres2decprot_attr(STM32MP1_SHRES_HASH1));
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etzpc_configure_decprot(STM32MP1_ETZPC_I2C4_ID,
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shres2decprot_attr(STM32MP1_SHRES_I2C4));
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etzpc_configure_decprot(STM32MP1_ETZPC_I2C6_ID,
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shres2decprot_attr(STM32MP1_SHRES_I2C6));
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etzpc_configure_decprot(STM32MP1_ETZPC_IWDG1_ID,
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shres2decprot_attr(STM32MP1_SHRES_IWDG1));
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etzpc_configure_decprot(STM32MP1_ETZPC_RNG1_ID,
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shres2decprot_attr(STM32MP1_SHRES_RNG1));
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etzpc_configure_decprot(STM32MP1_ETZPC_USART1_ID,
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shres2decprot_attr(STM32MP1_SHRES_USART1));
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etzpc_configure_decprot(STM32MP1_ETZPC_SPI6_ID,
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shres2decprot_attr(STM32MP1_SHRES_SPI6));
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}
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static void check_rcc_secure_configuration(void)
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{
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uint32_t n;
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uint32_t error = 0U;
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bool mckprot = stm32mp1_rcc_is_mckprot();
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bool secure = stm32mp1_rcc_is_secure();
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for (n = 0U; n < ARRAY_SIZE(shres_state); n++) {
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if (shres_state[n] != SHRES_SECURE) {
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continue;
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}
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if (!secure || (mckprot_protects_periph(n) && (!mckprot))) {
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2020-05-13 14:51:56 +01:00
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ERROR("RCC %s MCKPROT %s and %s secure\n",
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2020-05-13 09:07:45 +01:00
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secure ? "secure" : "non-secure",
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mckprot ? "set" : "not set",
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2020-05-13 14:51:56 +01:00
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shres2str_id(n));
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2020-05-13 09:07:45 +01:00
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error++;
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}
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}
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if (error != 0U) {
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panic();
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}
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}
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static void set_gpio_secure_configuration(void)
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{
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uint32_t pin;
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for (pin = 0U; pin < get_gpioz_nbpin(); pin++) {
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bool secure_state = periph_is_secure(STM32MP1_SHRES_GPIOZ(pin));
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set_gpio_secure_cfg(GPIO_BANK_Z, pin, secure_state);
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}
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}
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static void print_shared_resources_state(void)
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{
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unsigned int id;
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for (id = 0U; id < STM32MP1_SHRES_COUNT; id++) {
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switch (shres_state[id]) {
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case SHRES_SECURE:
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2020-05-13 14:51:56 +01:00
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INFO("stm32mp1 %s is secure\n", shres2str_id(id));
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2020-05-13 09:07:45 +01:00
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break;
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case SHRES_NON_SECURE:
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case SHRES_UNREGISTERED:
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2020-05-13 14:51:56 +01:00
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VERBOSE("stm32mp %s is non-secure\n", shres2str_id(id));
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2020-05-13 09:07:45 +01:00
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break;
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default:
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2020-05-13 14:51:56 +01:00
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VERBOSE("stm32mp %s is invalid\n", shres2str_id(id));
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2020-05-13 09:07:45 +01:00
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panic();
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}
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}
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}
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void stm32mp_lock_periph_registering(void)
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{
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registering_locked = true;
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print_shared_resources_state();
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check_rcc_secure_configuration();
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set_etzpc_secure_configuration();
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set_gpio_secure_configuration();
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}
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