186 lines
6.3 KiB
C
186 lines
6.3 KiB
C
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/*
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* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <assert.h>
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#include <console.h>
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#include <mmio.h>
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#include <plat_arm.h>
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#include <platform.h>
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#include <platform_def.h>
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#include <platform_sp_min.h>
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#define BL32_END (uintptr_t)(&__BL32_END__)
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#if USE_COHERENT_MEM
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/*
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* The next 2 constants identify the extents of the coherent memory region.
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* These addresses are used by the MMU setup code and therefore they must be
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* page-aligned. It is the responsibility of the linker script to ensure that
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* __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to
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* page-aligned addresses.
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*/
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#define BL32_COHERENT_RAM_BASE (uintptr_t)(&__COHERENT_RAM_START__)
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#define BL32_COHERENT_RAM_LIMIT (uintptr_t)(&__COHERENT_RAM_END__)
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#endif
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static entry_point_info_t bl33_image_ep_info;
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/* Weak definitions may be overridden in specific ARM standard platform */
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#pragma weak sp_min_early_platform_setup
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#pragma weak sp_min_platform_setup
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#pragma weak sp_min_plat_arch_setup
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#ifndef RESET_TO_SP_MIN
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#error (" RESET_TO_SP_MIN flag is expected to be set.")
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#endif
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/*******************************************************************************
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* Return a pointer to the 'entry_point_info' structure of the next image for the
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* security state specified. BL33 corresponds to the non-secure image type
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* while BL32 corresponds to the secure image type. A NULL pointer is returned
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* if the image does not exist.
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******************************************************************************/
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entry_point_info_t *sp_min_plat_get_bl33_ep_info(void)
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{
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entry_point_info_t *next_image_info;
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next_image_info = &bl33_image_ep_info;
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/*
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* None of the images on the ARM development platforms can have 0x0
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* as the entrypoint
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*/
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if (next_image_info->pc)
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return next_image_info;
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else
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return NULL;
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}
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/*******************************************************************************
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* Perform early platform setup. We expect SP_MIN is the first boot loader
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* image and RESET_TO_SP_MIN build option to be set.
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******************************************************************************/
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void arm_sp_min_early_platform_setup(void)
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{
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/* Initialize the console to provide early debug support */
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console_init(PLAT_ARM_BOOT_UART_BASE, PLAT_ARM_BOOT_UART_CLK_IN_HZ,
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ARM_CONSOLE_BAUDRATE);
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/* Populate entry point information for BL33 */
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SET_PARAM_HEAD(&bl33_image_ep_info,
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PARAM_EP,
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VERSION_1,
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0);
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/*
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* Tell SP_MIN where the non-trusted software image
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* is located and the entry state information
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*/
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#ifdef PRELOADED_BL33_BASE
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bl33_image_ep_info.pc = PRELOADED_BL33_BASE;
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#else
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bl33_image_ep_info.pc = plat_get_ns_image_entrypoint();
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#endif
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bl33_image_ep_info.spsr = arm_get_spsr_for_bl33_entry();
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SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
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}
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void sp_min_early_platform_setup(void)
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{
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arm_sp_min_early_platform_setup();
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/*
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* Initialize Interconnect for this cluster during cold boot.
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* No need for locks as no other CPU is active.
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*/
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plat_arm_interconnect_init();
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/*
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* Enable Interconnect coherency for the primary CPU's cluster.
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* Earlier bootloader stages might already do this (e.g. Trusted
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* Firmware's BL1 does it) but we can't assume so. There is no harm in
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* executing this code twice anyway.
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* Platform specific PSCI code will enable coherency for other
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* clusters.
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*/
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plat_arm_interconnect_enter_coherency();
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}
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/*******************************************************************************
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* Perform platform specific setup for SP_MIN
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******************************************************************************/
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void sp_min_platform_setup(void)
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{
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/* Initialize the GIC driver, cpu and distributor interfaces */
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plat_arm_gic_driver_init();
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plat_arm_gic_init();
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/*
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* Do initial security configuration to allow DRAM/device access
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* (if earlier BL has not already done so).
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* TODO: If RESET_TO_SP_MIN is not set, the security setup needs
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* to be skipped.
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*/
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plat_arm_security_setup();
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/* Enable and initialize the System level generic timer */
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mmio_write_32(ARM_SYS_CNTCTL_BASE + CNTCR_OFF,
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CNTCR_FCREQ(0) | CNTCR_EN);
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/* Allow access to the System counter timer module */
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arm_configure_sys_timer();
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/* Initialize power controller before setting up topology */
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plat_arm_pwrc_setup();
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}
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/*******************************************************************************
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* Perform the very early platform specific architectural setup here. At the
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* moment this only initializes the MMU
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******************************************************************************/
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void sp_min_plat_arch_setup(void)
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{
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arm_setup_page_tables(BL32_BASE,
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(BL32_END - BL32_BASE),
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BL_CODE_BASE,
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BL_CODE_LIMIT,
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BL_RO_DATA_BASE,
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BL_RO_DATA_LIMIT
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#if USE_COHERENT_MEM
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, BL32_COHERENT_RAM_BASE,
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BL32_COHERENT_RAM_LIMIT
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#endif
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);
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enable_mmu_secure(0);
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}
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