254 lines
8.8 KiB
C
254 lines
8.8 KiB
C
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/*
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* Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <arch_helpers.h>
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#include <assert.h>
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#include <debug.h>
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#include <gicv2.h>
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#include <platform_def.h>
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#include <platform.h>
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#include <psci.h>
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/*
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* The secure entry point to be used on warm reset.
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*/
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static unsigned long secure_entrypoint;
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/* Make composite power state parameter till power level 0 */
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#if PSCI_EXTENDED_STATE_ID
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#define qemu_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type) \
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(((lvl0_state) << PSTATE_ID_SHIFT) | \
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((type) << PSTATE_TYPE_SHIFT))
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#else
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#define qemu_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type) \
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(((lvl0_state) << PSTATE_ID_SHIFT) | \
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((pwr_lvl) << PSTATE_PWR_LVL_SHIFT) | \
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((type) << PSTATE_TYPE_SHIFT))
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#endif /* PSCI_EXTENDED_STATE_ID */
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#define qemu_make_pwrstate_lvl1(lvl1_state, lvl0_state, pwr_lvl, type) \
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(((lvl1_state) << PLAT_LOCAL_PSTATE_WIDTH) | \
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qemu_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type))
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/*
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* The table storing the valid idle power states. Ensure that the
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* array entries are populated in ascending order of state-id to
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* enable us to use binary search during power state validation.
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* The table must be terminated by a NULL entry.
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*/
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static const unsigned int qemu_pm_idle_states[] = {
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/* State-id - 0x01 */
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qemu_make_pwrstate_lvl1(PLAT_LOCAL_STATE_RUN, PLAT_LOCAL_STATE_RET,
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MPIDR_AFFLVL0, PSTATE_TYPE_STANDBY),
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/* State-id - 0x02 */
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qemu_make_pwrstate_lvl1(PLAT_LOCAL_STATE_RUN, PLAT_LOCAL_STATE_OFF,
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MPIDR_AFFLVL0, PSTATE_TYPE_POWERDOWN),
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/* State-id - 0x22 */
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qemu_make_pwrstate_lvl1(PLAT_LOCAL_STATE_OFF, PLAT_LOCAL_STATE_OFF,
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MPIDR_AFFLVL1, PSTATE_TYPE_POWERDOWN),
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0,
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};
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/*******************************************************************************
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* Platform handler called to check the validity of the power state
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* parameter. The power state parameter has to be a composite power state.
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******************************************************************************/
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static int qemu_validate_power_state(unsigned int power_state,
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psci_power_state_t *req_state)
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{
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unsigned int state_id;
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int i;
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assert(req_state);
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/*
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* Currently we are using a linear search for finding the matching
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* entry in the idle power state array. This can be made a binary
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* search if the number of entries justify the additional complexity.
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*/
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for (i = 0; !!qemu_pm_idle_states[i]; i++) {
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if (power_state == qemu_pm_idle_states[i])
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break;
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}
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/* Return error if entry not found in the idle state array */
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if (!qemu_pm_idle_states[i])
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return PSCI_E_INVALID_PARAMS;
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i = 0;
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state_id = psci_get_pstate_id(power_state);
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/* Parse the State ID and populate the state info parameter */
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while (state_id) {
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req_state->pwr_domain_state[i++] = state_id &
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PLAT_LOCAL_PSTATE_MASK;
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state_id >>= PLAT_LOCAL_PSTATE_WIDTH;
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}
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return PSCI_E_SUCCESS;
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}
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/*******************************************************************************
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* Platform handler called to check the validity of the non secure
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* entrypoint.
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******************************************************************************/
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static int qemu_validate_ns_entrypoint(uintptr_t entrypoint)
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{
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/*
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* Check if the non secure entrypoint lies within the non
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* secure DRAM.
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*/
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if ((entrypoint >= NS_DRAM0_BASE) &&
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(entrypoint < (NS_DRAM0_BASE + NS_DRAM0_SIZE)))
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return PSCI_E_SUCCESS;
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return PSCI_E_INVALID_ADDRESS;
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}
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/*******************************************************************************
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* Platform handler called when a CPU is about to enter standby.
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******************************************************************************/
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static void qemu_cpu_standby(plat_local_state_t cpu_state)
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{
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assert(cpu_state == PLAT_LOCAL_STATE_RET);
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/*
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* Enter standby state
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* dsb is good practice before using wfi to enter low power states
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*/
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dsb();
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wfi();
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}
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/*******************************************************************************
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* Platform handler called when a power domain is about to be turned on. The
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* mpidr determines the CPU to be turned on.
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******************************************************************************/
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static int qemu_pwr_domain_on(u_register_t mpidr)
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{
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int rc = PSCI_E_SUCCESS;
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unsigned pos = plat_core_pos_by_mpidr(mpidr);
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uint64_t *hold_base = (uint64_t *)PLAT_QEMU_HOLD_BASE;
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hold_base[pos] = PLAT_QEMU_HOLD_STATE_GO;
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sev();
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return rc;
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}
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/*******************************************************************************
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* Platform handler called when a power domain is about to be turned off. The
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* target_state encodes the power state that each level should transition to.
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******************************************************************************/
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void qemu_pwr_domain_off(const psci_power_state_t *target_state)
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{
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assert(0);
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}
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/*******************************************************************************
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* Platform handler called when a power domain is about to be suspended. The
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* target_state encodes the power state that each level should transition to.
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******************************************************************************/
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void qemu_pwr_domain_suspend(const psci_power_state_t *target_state)
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{
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assert(0);
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}
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/*******************************************************************************
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* Platform handler called when a power domain has just been powered on after
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* being turned off earlier. The target_state encodes the low power state that
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* each level has woken up from.
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******************************************************************************/
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void qemu_pwr_domain_on_finish(const psci_power_state_t *target_state)
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{
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assert(target_state->pwr_domain_state[MPIDR_AFFLVL0] ==
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PLAT_LOCAL_STATE_OFF);
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/* TODO: This setup is needed only after a cold boot */
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gicv2_pcpu_distif_init();
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/* Enable the gic cpu interface */
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gicv2_cpuif_enable();
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}
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/*******************************************************************************
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* Platform handler called when a power domain has just been powered on after
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* having been suspended earlier. The target_state encodes the low power state
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* that each level has woken up from.
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******************************************************************************/
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void qemu_pwr_domain_suspend_finish(const psci_power_state_t *target_state)
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{
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assert(0);
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}
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/*******************************************************************************
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* Platform handlers to shutdown/reboot the system
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******************************************************************************/
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static void __dead2 qemu_system_off(void)
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{
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ERROR("QEMU System Off: operation not handled.\n");
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panic();
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}
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static void __dead2 qemu_system_reset(void)
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{
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ERROR("QEMU System Reset: operation not handled.\n");
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panic();
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}
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static const plat_psci_ops_t plat_qemu_psci_pm_ops = {
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.cpu_standby = qemu_cpu_standby,
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.pwr_domain_on = qemu_pwr_domain_on,
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.pwr_domain_off = qemu_pwr_domain_off,
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.pwr_domain_suspend = qemu_pwr_domain_suspend,
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.pwr_domain_on_finish = qemu_pwr_domain_on_finish,
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.pwr_domain_suspend_finish = qemu_pwr_domain_suspend_finish,
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.system_off = qemu_system_off,
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.system_reset = qemu_system_reset,
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.validate_power_state = qemu_validate_power_state,
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.validate_ns_entrypoint = qemu_validate_ns_entrypoint
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};
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int plat_setup_psci_ops(uintptr_t sec_entrypoint,
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const plat_psci_ops_t **psci_ops)
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{
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uintptr_t *mailbox = (void *) PLAT_QEMU_TRUSTED_MAILBOX_BASE;
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*mailbox = sec_entrypoint;
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secure_entrypoint = (unsigned long) sec_entrypoint;
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*psci_ops = &plat_qemu_psci_pm_ops;
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return 0;
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}
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