89 lines
2.7 KiB
ArmAsm
89 lines
2.7 KiB
ArmAsm
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/*
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* Copyright (c) 2013, ARM Limited. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <platform.h>
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OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT)
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OUTPUT_ARCH(PLATFORM_LINKER_ARCH)
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MEMORY {
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/* RAM is read/write and Initialised */
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RAM (rwx): ORIGIN = TZRAM_BASE, LENGTH = TZRAM_SIZE
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}
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SECTIONS
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{
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. = BL31_BASE;
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BL31_RO ALIGN (4096): {
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*(entry_code)
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*(.text)
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*(.rodata)
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} >RAM
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BL31_STACKS ALIGN (4096): {
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. += 0x1000;
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*(tzfw_normal_stacks)
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} >RAM
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BL31_COHERENT_RAM ALIGN (4096): {
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*(tzfw_coherent_mem)
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/* . += 0x1000;*/
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/* Do we need to ensure at least 4k here? */
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. = ALIGN(4096);
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} >RAM
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__BL31_DATA_START__ = .;
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.bss ALIGN (4096): {
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*(.bss)
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*(COMMON)
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} >RAM
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.data : {
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*(.data)
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} >RAM
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__BL31_DATA_STOP__ = .;
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__BL31_RO_BASE__ = LOADADDR(BL31_RO);
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__BL31_RO_SIZE__ = SIZEOF(BL31_RO);
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__BL31_STACKS_BASE__ = LOADADDR(BL31_STACKS);
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__BL31_STACKS_SIZE__ = SIZEOF(BL31_STACKS);
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__BL31_COHERENT_RAM_BASE__ = LOADADDR(BL31_COHERENT_RAM);
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__BL31_COHERENT_RAM_SIZE__ = SIZEOF(BL31_COHERENT_RAM);
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__BL31_RW_BASE__ = __BL31_DATA_START__;
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__BL31_RW_SIZE__ = __BL31_DATA_STOP__ - __BL31_DATA_START__;
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}
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