124 lines
3.7 KiB
C
124 lines
3.7 KiB
C
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/*
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* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <arch.h>
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#include <arch_helpers.h>
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#include <assert.h>
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#include <denver.h>
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#include <debug.h>
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#include <flowctrl.h>
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#include <mmio.h>
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#include <platform_def.h>
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#include <pmc.h>
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#include <psci.h>
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#include <tegra_def.h>
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#include <tegra_private.h>
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/*
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* Register used to clear CPU reset signals. Each CPU has two reset
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* signals: CPU reset (3:0) and Core reset (19:16)
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*/
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#define CPU_CMPLX_RESET_CLR 0x344
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#define CPU_CORE_RESET_MASK 0x10001
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static int cpu_powergate_mask[PLATFORM_MAX_CPUS_PER_CLUSTER];
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int32_t tegra_soc_validate_power_state(unsigned int power_state)
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{
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/* Sanity check the requested afflvl */
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if (psci_get_pstate_type(power_state) == PSTATE_TYPE_STANDBY) {
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/*
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* It's possible to enter standby only on affinity level 0 i.e.
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* a cpu on Tegra. Ignore any other affinity level.
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*/
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if (psci_get_pstate_afflvl(power_state) != MPIDR_AFFLVL0)
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return PSCI_E_INVALID_PARAMS;
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}
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/* Sanity check the requested state id */
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if (psci_get_pstate_id(power_state) != PLAT_SYS_SUSPEND_STATE_ID) {
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ERROR("unsupported state id\n");
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return PSCI_E_NOT_SUPPORTED;
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}
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return PSCI_E_SUCCESS;
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}
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int tegra_soc_prepare_cpu_on(unsigned long mpidr)
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{
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int cpu = mpidr & MPIDR_CPU_MASK;
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uint32_t mask = CPU_CORE_RESET_MASK << cpu;
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if (cpu_powergate_mask[cpu] == 0) {
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/* Deassert CPU reset signals */
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mmio_write_32(TEGRA_CAR_RESET_BASE + CPU_CMPLX_RESET_CLR, mask);
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/* Power on CPU using PMC */
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tegra_pmc_cpu_on(cpu);
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/* Fill in the CPU powergate mask */
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cpu_powergate_mask[cpu] = 1;
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} else {
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/* Power on CPU using Flow Controller */
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tegra_fc_cpu_on(cpu);
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}
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return PSCI_E_SUCCESS;
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}
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int tegra_soc_prepare_cpu_off(unsigned long mpidr)
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{
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tegra_fc_cpu_off(mpidr & MPIDR_CPU_MASK);
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return PSCI_E_SUCCESS;
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}
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int tegra_soc_prepare_cpu_suspend(unsigned int id, unsigned int afflvl)
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{
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/* Nothing to be done for lower affinity levels */
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if (afflvl < MPIDR_AFFLVL2)
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return PSCI_E_SUCCESS;
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/* Enter system suspend state */
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tegra_pm_system_suspend_entry();
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/* Allow restarting CPU #1 using PMC on suspend exit */
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cpu_powergate_mask[1] = 0;
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/* Program FC to enter suspend state */
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tegra_fc_cpu_idle(read_mpidr());
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/* Suspend DCO operations */
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write_actlr_el1(id);
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return PSCI_E_SUCCESS;
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}
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