252 lines
6.2 KiB
C
252 lines
6.2 KiB
C
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/*
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* Copyright (C) 2018 Marvell International Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* https://spdx.org/licenses
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*/
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/* AP806 Marvell SoC driver */
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#include <ap_setup.h>
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#include <ccu.h>
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#include <cache_llc.h>
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#include <debug.h>
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#include <io_win.h>
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#include <mci.h>
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#include <mmio.h>
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#include <mvebu_def.h>
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#define SMMU_sACR (MVEBU_SMMU_BASE + 0x10)
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#define SMMU_sACR_PG_64K (1 << 16)
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#define CCU_GSPMU_CR (MVEBU_CCU_BASE(MVEBU_AP0) + \
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0x3F0)
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#define GSPMU_CPU_CONTROL (0x1 << 0)
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#define CCU_HTC_CR (MVEBU_CCU_BASE(MVEBU_AP0) + \
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0x200)
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#define CCU_SET_POC_OFFSET 5
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#define CCU_RGF(win) (MVEBU_CCU_BASE(MVEBU_AP0) + \
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0x90 + 4 * (win))
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#define DSS_CR0 (MVEBU_RFU_BASE + 0x100)
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#define DVM_48BIT_VA_ENABLE (1 << 21)
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/* Secure MoChi incoming access */
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#define SEC_MOCHI_IN_ACC_REG (MVEBU_RFU_BASE + 0x4738)
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#define SEC_MOCHI_IN_ACC_IHB0_EN (1)
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#define SEC_MOCHI_IN_ACC_IHB1_EN (1 << 3)
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#define SEC_MOCHI_IN_ACC_IHB2_EN (1 << 6)
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#define SEC_MOCHI_IN_ACC_PIDI_EN (1 << 9)
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#define SEC_IN_ACCESS_ENA_ALL_MASTERS (SEC_MOCHI_IN_ACC_IHB0_EN | \
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SEC_MOCHI_IN_ACC_IHB1_EN | \
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SEC_MOCHI_IN_ACC_IHB2_EN | \
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SEC_MOCHI_IN_ACC_PIDI_EN)
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/* SYSRST_OUTn Config definitions */
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#define MVEBU_SYSRST_OUT_CONFIG_REG (MVEBU_MISC_SOC_BASE + 0x4)
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#define WD_MASK_SYS_RST_OUT (1 << 2)
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/* Generic Timer System Controller */
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#define MVEBU_MSS_GTCR_REG (MVEBU_REGS_BASE + 0x581000)
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#define MVEBU_MSS_GTCR_ENABLE_BIT 0x1
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/*
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* AXI Configuration.
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*/
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/* Used for Units of AP-806 (e.g. SDIO and etc) */
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#define MVEBU_AXI_ATTR_BASE (MVEBU_REGS_BASE + 0x6F4580)
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#define MVEBU_AXI_ATTR_REG(index) (MVEBU_AXI_ATTR_BASE + \
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0x4 * index)
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enum axi_attr {
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AXI_SDIO_ATTR = 0,
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AXI_DFX_ATTR,
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AXI_MAX_ATTR,
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};
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static void apn_sec_masters_access_en(uint32_t enable)
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{
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uint32_t reg;
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/* Open/Close incoming access for all masters.
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* The access is disabled in trusted boot mode
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* Could only be done in EL3
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*/
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reg = mmio_read_32(SEC_MOCHI_IN_ACC_REG);
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if (enable)
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mmio_write_32(SEC_MOCHI_IN_ACC_REG, reg |
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SEC_IN_ACCESS_ENA_ALL_MASTERS);
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else
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mmio_write_32(SEC_MOCHI_IN_ACC_REG, reg &
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~SEC_IN_ACCESS_ENA_ALL_MASTERS);
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}
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static void setup_smmu(void)
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{
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uint32_t reg;
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/* Set the SMMU page size to 64 KB */
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reg = mmio_read_32(SMMU_sACR);
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reg |= SMMU_sACR_PG_64K;
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mmio_write_32(SMMU_sACR, reg);
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}
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static void apn806_errata_wa_init(void)
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{
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/*
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* ERRATA ID: RES-3033912 - Internal Address Space Init state causes
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* a hang upon accesses to [0xf070_0000, 0xf07f_ffff]
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* Workaround: Boot Firmware (ATF) should configure CCU_RGF_WIN(4) to
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* split [0x6e_0000, 0xff_ffff] to values [0x6e_0000, 0x6f_ffff] and
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* [0x80_0000, 0xff_ffff] that cause accesses to the
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* segment of [0xf070_0000, 0xf07f_ffff] to act as RAZWI.
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*/
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mmio_write_32(CCU_RGF(4), 0x37f9b809);
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mmio_write_32(CCU_RGF(5), 0x7ffa0009);
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}
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static void init_aurora2(void)
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{
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uint32_t reg;
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/* Enable GSPMU control by CPU */
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reg = mmio_read_32(CCU_GSPMU_CR);
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reg |= GSPMU_CPU_CONTROL;
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mmio_write_32(CCU_GSPMU_CR, reg);
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#if LLC_ENABLE
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/* Enable LLC for AP806 in exclusive mode */
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llc_enable(0, 1);
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/* Set point of coherency to DDR.
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* This is required by units which have
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* SW cache coherency
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*/
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reg = mmio_read_32(CCU_HTC_CR);
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reg |= (0x1 << CCU_SET_POC_OFFSET);
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mmio_write_32(CCU_HTC_CR, reg);
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#endif /* LLC_ENABLE */
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apn806_errata_wa_init();
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}
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/* MCIx indirect access register are based by default at 0xf4000000/0xf6000000
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* to avoid conflict of internal registers of units connected via MCIx, which
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* can be based on the same address (i.e CP1 base is also 0xf4000000),
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* the following routines remaps the MCIx indirect bases to another domain
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*/
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static void mci_remap_indirect_access_base(void)
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{
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uint32_t mci;
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for (mci = 0; mci < MCI_MAX_UNIT_ID; mci++)
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mmio_write_32(MCIX4_REG_START_ADDRESS_REG(mci),
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MVEBU_MCI_REG_BASE_REMAP(mci) >>
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MCI_REMAP_OFF_SHIFT);
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}
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static void apn806_axi_attr_init(void)
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{
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uint32_t index, data;
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/* Initialize AXI attributes for APN806 */
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/* Go over the AXI attributes and set Ax-Cache and Ax-Domain */
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for (index = 0; index < AXI_MAX_ATTR; index++) {
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switch (index) {
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/* DFX works with no coherent only -
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* there's no option to configure the Ax-Cache and Ax-Domain
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*/
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case AXI_DFX_ATTR:
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continue;
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default:
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/* Set Ax-Cache as cacheable, no allocate, modifiable,
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* bufferable
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* The values are different because Read & Write
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* definition is different in Ax-Cache
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*/
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data = mmio_read_32(MVEBU_AXI_ATTR_REG(index));
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data &= ~MVEBU_AXI_ATTR_ARCACHE_MASK;
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data |= (CACHE_ATTR_WRITE_ALLOC |
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CACHE_ATTR_CACHEABLE |
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CACHE_ATTR_BUFFERABLE) <<
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MVEBU_AXI_ATTR_ARCACHE_OFFSET;
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data &= ~MVEBU_AXI_ATTR_AWCACHE_MASK;
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data |= (CACHE_ATTR_READ_ALLOC |
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CACHE_ATTR_CACHEABLE |
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CACHE_ATTR_BUFFERABLE) <<
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MVEBU_AXI_ATTR_AWCACHE_OFFSET;
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/* Set Ax-Domain as Outer domain */
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data &= ~MVEBU_AXI_ATTR_ARDOMAIN_MASK;
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data |= DOMAIN_OUTER_SHAREABLE <<
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MVEBU_AXI_ATTR_ARDOMAIN_OFFSET;
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data &= ~MVEBU_AXI_ATTR_AWDOMAIN_MASK;
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data |= DOMAIN_OUTER_SHAREABLE <<
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MVEBU_AXI_ATTR_AWDOMAIN_OFFSET;
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mmio_write_32(MVEBU_AXI_ATTR_REG(index), data);
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}
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}
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}
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static void dss_setup(void)
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{
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/* Enable 48-bit VA */
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mmio_setbits_32(DSS_CR0, DVM_48BIT_VA_ENABLE);
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}
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void misc_soc_configurations(void)
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{
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uint32_t reg;
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/* Un-mask Watchdog reset from influencing the SYSRST_OUTn.
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* Otherwise, upon WD timeout, the WD reset signal won't trigger reset
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*/
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reg = mmio_read_32(MVEBU_SYSRST_OUT_CONFIG_REG);
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reg &= ~(WD_MASK_SYS_RST_OUT);
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mmio_write_32(MVEBU_SYSRST_OUT_CONFIG_REG, reg);
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}
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void ap_init(void)
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{
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/* Setup Aurora2. */
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init_aurora2();
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/* configure MCI mapping */
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mci_remap_indirect_access_base();
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/* configure IO_WIN windows */
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init_io_win(MVEBU_AP0);
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/* configure CCU windows */
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init_ccu(MVEBU_AP0);
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/* configure DSS */
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dss_setup();
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/* configure the SMMU */
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setup_smmu();
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/* Open APN incoming access for all masters */
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apn_sec_masters_access_en(1);
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/* configure axi for APN*/
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apn806_axi_attr_init();
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/* misc configuration of the SoC */
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misc_soc_configurations();
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}
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void ap_ble_init(void)
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{
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}
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int ap_get_count(void)
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{
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return 1;
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}
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