2013-10-25 09:08:21 +01:00
|
|
|
/*
|
2014-01-14 18:17:09 +00:00
|
|
|
* Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
|
2013-10-25 09:08:21 +01:00
|
|
|
*
|
|
|
|
* Redistribution and use in source and binary forms, with or without
|
|
|
|
* modification, are permitted provided that the following conditions are met:
|
|
|
|
*
|
|
|
|
* Redistributions of source code must retain the above copyright notice, this
|
|
|
|
* list of conditions and the following disclaimer.
|
|
|
|
*
|
|
|
|
* Redistributions in binary form must reproduce the above copyright notice,
|
|
|
|
* this list of conditions and the following disclaimer in the documentation
|
|
|
|
* and/or other materials provided with the distribution.
|
|
|
|
*
|
|
|
|
* Neither the name of ARM nor the names of its contributors may be used
|
|
|
|
* to endorse or promote products derived from this software without specific
|
|
|
|
* prior written permission.
|
|
|
|
*
|
|
|
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
|
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
|
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
|
|
|
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
|
|
|
|
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
|
|
|
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
|
|
|
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
|
|
|
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
|
|
|
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
|
|
|
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
|
|
|
* POSSIBILITY OF SUCH DAMAGE.
|
|
|
|
*/
|
|
|
|
|
2014-04-09 13:14:54 +01:00
|
|
|
#include <arch.h>
|
2013-10-25 09:08:21 +01:00
|
|
|
#include <arch_helpers.h>
|
|
|
|
#include <assert.h>
|
2014-04-09 13:14:54 +01:00
|
|
|
#include <bl_common.h>
|
|
|
|
#include <bl31.h>
|
|
|
|
#include <platform.h>
|
2013-10-25 09:08:21 +01:00
|
|
|
|
|
|
|
/*******************************************************************************
|
|
|
|
* This duplicates what the primary cpu did after a cold boot in BL1. The same
|
|
|
|
* needs to be done when a cpu is hotplugged in. This function could also over-
|
|
|
|
* ride any EL3 setup done by BL1 as this code resides in rw memory.
|
|
|
|
******************************************************************************/
|
|
|
|
void bl31_arch_setup(void)
|
|
|
|
{
|
|
|
|
unsigned long tmp_reg = 0;
|
2014-03-31 11:25:18 +01:00
|
|
|
uint64_t counter_freq;
|
2013-10-25 09:08:21 +01:00
|
|
|
|
2014-04-24 15:33:24 +01:00
|
|
|
/* Enable alignment checks */
|
2014-03-11 17:41:00 +00:00
|
|
|
tmp_reg = read_sctlr_el3();
|
2013-10-25 09:08:21 +01:00
|
|
|
tmp_reg |= (SCTLR_A_BIT | SCTLR_SA_BIT);
|
2014-03-11 17:41:00 +00:00
|
|
|
write_sctlr_el3(tmp_reg);
|
2013-10-25 09:08:21 +01:00
|
|
|
|
|
|
|
/*
|
2014-06-04 21:10:52 +01:00
|
|
|
* Route external abort and SError interrupts to EL3
|
|
|
|
* other SCR bits will be configured before exiting to a lower exception
|
|
|
|
* level
|
2013-10-25 09:08:21 +01:00
|
|
|
*/
|
2014-06-04 21:10:52 +01:00
|
|
|
tmp_reg = SCR_RES1_BITS | SCR_EA_BIT;
|
2013-10-25 09:08:21 +01:00
|
|
|
write_scr(tmp_reg);
|
|
|
|
|
2013-11-18 17:26:59 +00:00
|
|
|
/*
|
|
|
|
* Enable SError and Debug exceptions
|
|
|
|
*/
|
|
|
|
enable_serror();
|
|
|
|
enable_debug_exceptions();
|
|
|
|
|
2014-03-31 10:44:09 +01:00
|
|
|
/* Program the counter frequency */
|
2014-03-31 11:25:18 +01:00
|
|
|
counter_freq = plat_get_syscnt_freq();
|
|
|
|
write_cntfrq_el0(counter_freq);
|
2013-10-25 09:08:21 +01:00
|
|
|
}
|