215 lines
6.0 KiB
C
215 lines
6.0 KiB
C
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/*
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* Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <arch_helpers.h>
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#include <common/debug.h>
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#include <denver.h>
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#include <lib/mmio.h>
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#include <mce_private.h>
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#include <errno.h>
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extern void nvg_set_request_data(uint64_t req, uint64_t data);
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extern void nvg_set_request(uint64_t req);
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extern uint64_t nvg_get_result(void);
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int nvg_enter_cstate(uint32_t ari_base, uint32_t state, uint32_t wake_time)
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{
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/* check for allowed power state */
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if (state != TEGRA_ARI_CORE_C0 && state != TEGRA_ARI_CORE_C1 &&
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state != TEGRA_ARI_CORE_C6 && state != TEGRA_ARI_CORE_C7) {
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ERROR("%s: unknown cstate (%d)\n", __func__, state);
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return EINVAL;
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}
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/* time (TSC ticks) until the core is expected to get a wake event */
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nvg_set_request_data(TEGRA_NVG_CHANNEL_WAKE_TIME, wake_time);
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/* set the core cstate */
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write_actlr_el1(state);
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return 0;
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}
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/*
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* This request allows updating of CLUSTER_CSTATE, CCPLEX_CSTATE and
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* SYSTEM_CSTATE values.
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*/
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int nvg_update_cstate_info(uint32_t ari_base, uint32_t cluster, uint32_t ccplex,
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uint32_t system, uint8_t sys_state_force, uint32_t wake_mask,
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uint8_t update_wake_mask)
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{
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uint64_t val = 0;
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/* update CLUSTER_CSTATE? */
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if (cluster)
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val |= (cluster & CLUSTER_CSTATE_MASK) |
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CLUSTER_CSTATE_UPDATE_BIT;
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/* update CCPLEX_CSTATE? */
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if (ccplex)
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val |= (ccplex & CCPLEX_CSTATE_MASK) << CCPLEX_CSTATE_SHIFT |
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CCPLEX_CSTATE_UPDATE_BIT;
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/* update SYSTEM_CSTATE? */
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if (system)
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val |= ((system & SYSTEM_CSTATE_MASK) << SYSTEM_CSTATE_SHIFT) |
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((sys_state_force << SYSTEM_CSTATE_FORCE_UPDATE_SHIFT) |
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SYSTEM_CSTATE_UPDATE_BIT);
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/* update wake mask value? */
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if (update_wake_mask)
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val |= CSTATE_WAKE_MASK_UPDATE_BIT;
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/* set the wake mask */
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val &= CSTATE_WAKE_MASK_CLEAR;
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val |= ((uint64_t)wake_mask << CSTATE_WAKE_MASK_SHIFT);
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/* set the updated cstate info */
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nvg_set_request_data(TEGRA_NVG_CHANNEL_CSTATE_INFO, val);
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return 0;
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}
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int nvg_update_crossover_time(uint32_t ari_base, uint32_t type, uint32_t time)
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{
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/* sanity check crossover type */
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if (type > TEGRA_ARI_CROSSOVER_CCP3_SC1)
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return EINVAL;
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/*
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* The crossover threshold limit types start from
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* TEGRA_CROSSOVER_TYPE_C1_C6 to TEGRA_CROSSOVER_TYPE_CCP3_SC7. The
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* command indices for updating the threshold can be generated
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* by adding the type to the NVG_SET_THRESHOLD_CROSSOVER_C1_C6
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* command index.
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*/
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nvg_set_request_data(TEGRA_NVG_CHANNEL_CROSSOVER_C1_C6 + type,
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(uint64_t)time);
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return 0;
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}
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uint64_t nvg_read_cstate_stats(uint32_t ari_base, uint32_t state)
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{
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/* sanity check state */
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if (state == 0)
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return EINVAL;
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/*
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* The cstate types start from NVG_READ_CSTATE_STATS_SC7_ENTRIES
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* to NVG_GET_LAST_CSTATE_ENTRY_A57_3. The command indices for
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* reading the threshold can be generated by adding the type to
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* the NVG_CLEAR_CSTATE_STATS command index.
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*/
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nvg_set_request(TEGRA_NVG_CHANNEL_CSTATE_STATS_CLEAR + state);
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return (int64_t)nvg_get_result();
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}
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int nvg_write_cstate_stats(uint32_t ari_base, uint32_t state, uint32_t stats)
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{
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uint64_t val;
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/*
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* The only difference between a CSTATE_STATS_WRITE and
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* CSTATE_STATS_READ is the usage of the 63:32 in the request.
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* 63:32 are set to '0' for a read, while a write contains the
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* actual stats value to be written.
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*/
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val = ((uint64_t)stats << MCE_CSTATE_STATS_TYPE_SHIFT) | state;
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/*
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* The cstate types start from NVG_READ_CSTATE_STATS_SC7_ENTRIES
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* to NVG_GET_LAST_CSTATE_ENTRY_A57_3. The command indices for
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* reading the threshold can be generated by adding the type to
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* the NVG_CLEAR_CSTATE_STATS command index.
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*/
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nvg_set_request_data(TEGRA_NVG_CHANNEL_CSTATE_STATS_CLEAR + state, val);
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return 0;
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}
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int nvg_is_ccx_allowed(uint32_t ari_base, uint32_t state, uint32_t wake_time)
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{
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/* This does not apply to the Denver cluster */
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return 0;
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}
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int nvg_is_sc7_allowed(uint32_t ari_base, uint32_t state, uint32_t wake_time)
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{
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uint64_t val;
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/* check for allowed power state */
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if (state != TEGRA_ARI_CORE_C0 && state != TEGRA_ARI_CORE_C1 &&
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state != TEGRA_ARI_CORE_C6 && state != TEGRA_ARI_CORE_C7) {
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ERROR("%s: unknown cstate (%d)\n", __func__, state);
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return EINVAL;
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}
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/*
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* Request format -
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* 63:32 = wake time
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* 31:0 = C-state for this core
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*/
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val = ((uint64_t)wake_time << MCE_SC7_WAKE_TIME_SHIFT) |
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(state & MCE_SC7_ALLOWED_MASK);
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/* issue command to check if SC7 is allowed */
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nvg_set_request_data(TEGRA_NVG_CHANNEL_IS_SC7_ALLOWED, val);
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/* 1 = SC7 allowed, 0 = SC7 not allowed */
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return !!nvg_get_result();
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}
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int nvg_online_core(uint32_t ari_base, uint32_t core)
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{
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int cpu = read_mpidr() & MPIDR_CPU_MASK;
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int impl = (read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK;
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/* sanity check code id */
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if ((core >= MCE_CORE_ID_MAX) || (cpu == core)) {
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ERROR("%s: unsupported core id (%d)\n", __func__, core);
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return EINVAL;
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}
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/*
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* The Denver cluster has 2 CPUs only - 0, 1.
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*/
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if (impl == DENVER_IMPL && ((core == 2) || (core == 3))) {
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ERROR("%s: unknown core id (%d)\n", __func__, core);
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return EINVAL;
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}
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/* get a core online */
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nvg_set_request_data(TEGRA_NVG_CHANNEL_ONLINE_CORE, core & MCE_CORE_ID_MASK);
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return 0;
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}
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int nvg_cc3_ctrl(uint32_t ari_base, uint32_t freq, uint32_t volt, uint8_t enable)
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{
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int val;
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/*
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* If the enable bit is cleared, Auto-CC3 will be disabled by setting
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* the SW visible voltage/frequency request registers for all non
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* floorswept cores valid independent of StandbyWFI and disabling
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* the IDLE voltage/frequency request register. If set, Auto-CC3
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* will be enabled by setting the ARM SW visible voltage/frequency
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* request registers for all non floorswept cores to be enabled by
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* StandbyWFI or the equivalent signal, and always keeping the IDLE
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* voltage/frequency request register enabled.
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*/
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val = (((freq & MCE_AUTO_CC3_FREQ_MASK) << MCE_AUTO_CC3_FREQ_SHIFT) |\
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((volt & MCE_AUTO_CC3_VTG_MASK) << MCE_AUTO_CC3_VTG_SHIFT) |\
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(enable ? MCE_AUTO_CC3_ENABLE_BIT : 0));
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nvg_set_request_data(TEGRA_NVG_CHANNEL_CC3_CTRL, val);
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return 0;
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}
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