96 lines
3.8 KiB
C
96 lines
3.8 KiB
C
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/*
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* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <arch_helpers.h>
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#include <assert.h>
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#include <bl_common.h>
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#include <debug.h>
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#include <gic_v2.h>
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#include <interrupt_mgmt.h>
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#include <platform.h>
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#include <stdint.h>
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#include <tegra_private.h>
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#include <tegra_def.h>
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/*******************************************************************************
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* Place the cpu interface in a state where it can never make a cpu exit wfi as
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* as result of an asserted interrupt. This is critical for powering down a cpu
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******************************************************************************/
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void tegra_gic_cpuif_deactivate(void)
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{
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unsigned int val;
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/* Disable secure, non-secure interrupts and disable their bypass */
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val = gicc_read_ctlr(TEGRA_GICC_BASE);
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val &= ~(ENABLE_GRP0 | ENABLE_GRP1);
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val |= FIQ_BYP_DIS_GRP1 | FIQ_BYP_DIS_GRP0;
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val |= IRQ_BYP_DIS_GRP0 | IRQ_BYP_DIS_GRP1;
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gicc_write_ctlr(TEGRA_GICC_BASE, val);
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}
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/*******************************************************************************
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* Enable secure interrupts and set the priority mask register to allow all
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* interrupts to trickle in.
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******************************************************************************/
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static void tegra_gic_cpuif_setup(unsigned int gicc_base)
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{
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gicc_write_ctlr(gicc_base, ENABLE_GRP0 | ENABLE_GRP1);
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gicc_write_pmr(gicc_base, GIC_PRI_MASK);
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}
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/*******************************************************************************
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* Global gic distributor setup which will be done by the primary cpu after a
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* cold boot. It marks out the non secure SPIs, PPIs & SGIs and enables them.
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* It then enables the secure GIC distributor interface.
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******************************************************************************/
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static void tegra_gic_distif_setup(unsigned int gicd_base)
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{
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unsigned int ctr, num_ints;
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/*
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* Mark out non-secure interrupts. Calculate number of
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* IGROUPR registers to consider. Will be equal to the
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* number of IT_LINES
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*/
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num_ints = gicd_read_typer(gicd_base) & IT_LINES_NO_MASK;
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num_ints++;
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for (ctr = 0; ctr < num_ints; ctr++)
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gicd_write_igroupr(gicd_base, ctr << IGROUPR_SHIFT, ~0);
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/* enable distributor */
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gicd_write_ctlr(gicd_base, ENABLE_GRP0 | ENABLE_GRP1);
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}
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void tegra_gic_setup(void)
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{
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tegra_gic_cpuif_setup(TEGRA_GICC_BASE);
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tegra_gic_distif_setup(TEGRA_GICD_BASE);
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}
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