2020-11-18 16:46:32 +00:00
|
|
|
/*
|
|
|
|
* Copyright (c) 2021, ARM Limited. All rights reserved.
|
|
|
|
*
|
|
|
|
* SPDX-License-Identifier: BSD-3-Clause
|
|
|
|
*/
|
|
|
|
|
2021-05-18 21:23:31 +01:00
|
|
|
#ifndef CORTEX_A510_H
|
|
|
|
#define CORTEX_A510_H
|
2020-11-18 16:46:32 +00:00
|
|
|
|
2021-05-18 21:23:31 +01:00
|
|
|
#define CORTEX_A510_MIDR U(0x410FD460)
|
2020-11-18 16:46:32 +00:00
|
|
|
|
|
|
|
/*******************************************************************************
|
|
|
|
* CPU Extended Control register specific definitions
|
|
|
|
******************************************************************************/
|
2021-05-18 21:23:31 +01:00
|
|
|
#define CORTEX_A510_CPUECTLR_EL1 S3_0_C15_C1_4
|
2020-11-18 16:46:32 +00:00
|
|
|
|
|
|
|
/*******************************************************************************
|
|
|
|
* CPU Power Control register specific definitions
|
|
|
|
******************************************************************************/
|
2021-05-18 21:23:31 +01:00
|
|
|
#define CORTEX_A510_CPUPWRCTLR_EL1 S3_0_C15_C2_7
|
|
|
|
#define CORTEX_A510_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
|
2020-11-18 16:46:32 +00:00
|
|
|
|
2021-05-18 21:23:31 +01:00
|
|
|
#endif /* CORTEX_A510_H */
|