2022-03-07 04:04:59 +00:00
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/*
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2022-02-28 07:24:59 +00:00
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* Copyright (c) 2020-2022, ARM Limited and Contributors. All rights reserved.
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2022-03-07 04:04:59 +00:00
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* Copyright (c) 2020-2022, Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef PLAT_SOCFPGA_DEF_H
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#define PLAT_SOCFPGA_DEF_H
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#include <platform_def.h>
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/* Platform Setting */
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#define PLATFORM_MODEL PLAT_SOCFPGA_N5X
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#define BOOT_SOURCE BOOT_SOURCE_SDMMC
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2022-02-28 07:24:59 +00:00
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/* FPGA config helpers */
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#define INTEL_SIP_SMC_FPGA_CONFIG_ADDR 0x400000
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#define INTEL_SIP_SMC_FPGA_CONFIG_SIZE 0x2000000
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2022-03-07 04:04:59 +00:00
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/* Register Mapping */
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2022-05-05 10:07:21 +01:00
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#define SOCFPGA_CCU_NOC_REG_BASE U(0xf7000000)
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#define SOCFPGA_F2SDRAMMGR_REG_BASE U(0xf8024000)
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2022-03-07 04:04:59 +00:00
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#define SOCFPGA_MMC_REG_BASE U(0xff808000)
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#define SOCFPGA_RSTMGR_REG_BASE U(0xffd11000)
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#define SOCFPGA_SYSMGR_REG_BASE U(0xffd12000)
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#define SOCFPGA_L4_PER_SCR_REG_BASE U(0xffd21000)
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#define SOCFPGA_L4_SYS_SCR_REG_BASE U(0xffd21100)
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#define SOCFPGA_SOC2FPGA_SCR_REG_BASE U(0xffd21200)
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#define SOCFPGA_LWSOC2FPGA_SCR_REG_BASE U(0xffd21300)
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2022-04-06 03:19:16 +01:00
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/* Platform specific system counter */
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/*
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* In N5X the clk init is done in Uboot SPL.
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* BL31 shall bypass the clk init and only provides other APIs.
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*/
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#define PLAT_SYS_COUNTER_FREQ_IN_MHZ (400)
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2022-03-07 04:04:59 +00:00
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#endif /* PLAT_SOCFPGA_DEF_H */
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