arm-trusted-firmware/lib/xlat_tables_v2/xlat_tables_common.c

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/*
* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <arch.h>
#include <arch_helpers.h>
#include <assert.h>
#include <cassert.h>
#include <common_def.h>
#include <debug.h>
#include <errno.h>
#include <platform_def.h>
#include <string.h>
#include <types.h>
#include <utils.h>
#include <xlat_tables_v2.h>
#ifdef AARCH32
# include "aarch32/xlat_tables_arch.h"
#else
# include "aarch64/xlat_tables_arch.h"
#endif
#include "xlat_tables_private.h"
/*
* Private variables used by the TF
*/
static mmap_region_t tf_mmap[MAX_MMAP_REGIONS + 1];
static uint64_t tf_xlat_tables[MAX_XLAT_TABLES][XLAT_TABLE_ENTRIES]
__aligned(XLAT_TABLE_SIZE) __section("xlat_table");
static uint64_t tf_base_xlat_table[NUM_BASE_LEVEL_ENTRIES]
__aligned(NUM_BASE_LEVEL_ENTRIES * sizeof(uint64_t));
#if PLAT_XLAT_TABLES_DYNAMIC
static int xlat_tables_mapped_regions[MAX_XLAT_TABLES];
#endif /* PLAT_XLAT_TABLES_DYNAMIC */
xlat_ctx_t tf_xlat_ctx = {
.pa_max_address = PLAT_PHY_ADDR_SPACE_SIZE - 1,
.va_max_address = PLAT_VIRT_ADDR_SPACE_SIZE - 1,
.mmap = tf_mmap,
.mmap_num = MAX_MMAP_REGIONS,
.tables = tf_xlat_tables,
.tables_num = MAX_XLAT_TABLES,
#if PLAT_XLAT_TABLES_DYNAMIC
.tables_mapped_regions = xlat_tables_mapped_regions,
#endif /* PLAT_XLAT_TABLES_DYNAMIC */
.base_table = tf_base_xlat_table,
.base_table_entries = NUM_BASE_LEVEL_ENTRIES,
.max_pa = 0,
.max_va = 0,
.next_table = 0,
.base_level = XLAT_TABLE_LEVEL_BASE,
.initialized = 0
};
void mmap_add_region(unsigned long long base_pa, uintptr_t base_va,
size_t size, mmap_attr_t attr)
{
mmap_region_t mm = {
.base_va = base_va,
.base_pa = base_pa,
.size = size,
.attr = attr,
};
mmap_add_region_ctx(&tf_xlat_ctx, (mmap_region_t *)&mm);
}
void mmap_add(const mmap_region_t *mm)
{
while (mm->size) {
mmap_add_region_ctx(&tf_xlat_ctx, (mmap_region_t *)mm);
mm++;
}
}
#if PLAT_XLAT_TABLES_DYNAMIC
int mmap_add_dynamic_region(unsigned long long base_pa,
uintptr_t base_va, size_t size, mmap_attr_t attr)
{
mmap_region_t mm = {
.base_va = base_va,
.base_pa = base_pa,
.size = size,
.attr = attr,
};
return mmap_add_dynamic_region_ctx(&tf_xlat_ctx, &mm);
}
int mmap_remove_dynamic_region(uintptr_t base_va, size_t size)
{
return mmap_remove_dynamic_region_ctx(&tf_xlat_ctx, base_va, size);
}
#endif /* PLAT_XLAT_TABLES_DYNAMIC */
void init_xlat_tables(void)
{
assert(!is_mmu_enabled());
assert(!tf_xlat_ctx.initialized);
print_mmap(tf_xlat_ctx.mmap);
Fix execute-never permissions in xlat tables libs Translation regimes that only support one virtual address space (such as the ones for EL2 and EL3) can flag memory regions as execute-never by setting to 1 the XN bit in the Upper Attributes field in the translation tables descriptors. Translation regimes that support two different virtual address spaces (such as the one shared by EL1 and EL0) use bits PXN and UXN instead. The Trusted Firmware runs at EL3 and EL1, it has to handle translation tables of both translation regimes, but the previous code handled both regimes the same way, as if both had only 1 VA range. When trying to set a descriptor as execute-never it would set the XN bit correctly in EL3, but it would set the XN bit in EL1 as well. XN is at the same bit position as UXN, which means that EL0 was being prevented from executing code at this region, not EL1 as the code intended. Therefore, the PXN bit was unset to 0 all the time. The result is that, in AArch64 mode, read-only data sections of BL2 weren't protected from being executed. This patch adds support of translation regimes with two virtual address spaces to both versions of the translation tables library, fixing the execute-never permissions for translation tables in EL1. The library currently does not support initializing translation tables for EL0 software, therefore it does not set/unset the UXN bit. If EL1 software needs to initialize translation tables for EL0 software, it should use a different library instead. Change-Id: If27588f9820ff42988851d90dc92801c8ecbe0c9 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2017-04-27 13:30:22 +01:00
tf_xlat_ctx.execute_never_mask =
xlat_arch_get_xn_desc(xlat_arch_current_el());
init_xlation_table(&tf_xlat_ctx);
xlat_tables_print(&tf_xlat_ctx);
assert(tf_xlat_ctx.max_va <= PLAT_VIRT_ADDR_SPACE_SIZE - 1);
assert(tf_xlat_ctx.max_pa <= PLAT_PHY_ADDR_SPACE_SIZE - 1);
init_xlat_tables_arch(tf_xlat_ctx.max_pa);
}
#ifdef AARCH32
void enable_mmu_secure(unsigned int flags)
{
enable_mmu_arch(flags, tf_xlat_ctx.base_table);
}
#else
void enable_mmu_el1(unsigned int flags)
{
enable_mmu_arch(flags, tf_xlat_ctx.base_table);
}
void enable_mmu_el3(unsigned int flags)
{
enable_mmu_arch(flags, tf_xlat_ctx.base_table);
}
#endif /* AARCH32 */