193 lines
7.1 KiB
C
193 lines
7.1 KiB
C
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/*
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* Copyright (c) 2019, Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <arch_helpers.h>
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#include <assert.h>
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#include <drivers/delay_timer.h>
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#include <lib/mmio.h>
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#include <platform_def.h>
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#include <platform_private.h>
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#include "s10_clock_manager.h"
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#include "s10_handoff.h"
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void wait_pll_lock(void)
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{
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uint32_t data;
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do {
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data = mmio_read_32(ALT_CLKMGR + ALT_CLKMGR_STAT);
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} while ((ALT_CLKMGR_STAT_MAINPLLLOCKED(data) == 0) ||
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(ALT_CLKMGR_STAT_PERPLLLOCKED(data) == 0));
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}
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void wait_fsm(void)
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{
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uint32_t data;
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do {
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data = mmio_read_32(ALT_CLKMGR + ALT_CLKMGR_STAT);
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} while (ALT_CLKMGR_STAT_BUSY(data) == ALT_CLKMGR_STAT_BUSY_E_BUSY);
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}
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void config_clkmgr_handoff(handoff *hoff_ptr)
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{
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uint32_t m_div, refclk_div, mscnt, hscnt;
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/* Bypass all mainpllgrp's clocks */
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mmio_write_32(ALT_CLKMGR_MAINPLL +
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ALT_CLKMGR_MAINPLL_BYPASS,
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0x7);
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wait_fsm();
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/* Bypass all perpllgrp's clocks */
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mmio_write_32(ALT_CLKMGR_PERPLL +
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ALT_CLKMGR_PERPLL_BYPASS,
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0x7f);
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wait_fsm();
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/* Setup main PLL dividers */
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m_div = ALT_CLKMGR_MAINPLL_FDBCK_MDIV(hoff_ptr->main_pll_fdbck);
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refclk_div = ALT_CLKMGR_MAINPLL_PLLGLOB_REFCLKDIV(
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hoff_ptr->main_pll_pllglob);
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mscnt = 200 / ((6 + m_div) / refclk_div);
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hscnt = (m_div + 6) * mscnt / refclk_div - 9;
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mmio_write_32(ALT_CLKMGR_MAINPLL + ALT_CLKMGR_MAINPLL_PLLGLOB,
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hoff_ptr->main_pll_pllglob);
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mmio_write_32(ALT_CLKMGR_MAINPLL + ALT_CLKMGR_MAINPLL_FDBCK,
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hoff_ptr->main_pll_fdbck);
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mmio_write_32(ALT_CLKMGR_MAINPLL + ALT_CLKMGR_MAINPLL_VCOCALIB,
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ALT_CLKMGR_MAINPLL_VCOCALIB_HSCNT_SET(hscnt) |
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ALT_CLKMGR_MAINPLL_VCOCALIB_MSCNT_SET(mscnt));
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mmio_write_32(ALT_CLKMGR_MAINPLL + ALT_CLKMGR_MAINPLL_PLLC0,
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hoff_ptr->main_pll_pllc0);
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mmio_write_32(ALT_CLKMGR_MAINPLL + ALT_CLKMGR_MAINPLL_PLLC1,
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hoff_ptr->main_pll_pllc1);
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mmio_write_32(ALT_CLKMGR_MAINPLL + ALT_CLKMGR_MAINPLL_NOCDIV,
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hoff_ptr->main_pll_nocdiv);
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/* Setup peripheral PLL dividers */
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m_div = ALT_CLKMGR_PERPLL_FDBCK_MDIV(hoff_ptr->per_pll_fdbck);
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refclk_div = ALT_CLKMGR_PERPLL_PLLGLOB_REFCLKDIV(
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hoff_ptr->per_pll_pllglob);
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mscnt = 200 / ((6 + m_div) / refclk_div);
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hscnt = (m_div + 6) * mscnt / refclk_div - 9;
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mmio_write_32(ALT_CLKMGR_PERPLL + ALT_CLKMGR_PERPLL_PLLGLOB,
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hoff_ptr->per_pll_pllglob);
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mmio_write_32(ALT_CLKMGR_PERPLL + ALT_CLKMGR_PERPLL_FDBCK,
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hoff_ptr->per_pll_fdbck);
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mmio_write_32(ALT_CLKMGR_PERPLL + ALT_CLKMGR_PERPLL_VCOCALIB,
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ALT_CLKMGR_PERPLL_VCOCALIB_HSCNT_SET(hscnt) |
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ALT_CLKMGR_PERPLL_VCOCALIB_MSCNT_SET(mscnt));
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mmio_write_32(ALT_CLKMGR_PERPLL + ALT_CLKMGR_PERPLL_PLLC0,
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hoff_ptr->per_pll_pllc0);
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mmio_write_32(ALT_CLKMGR_PERPLL + ALT_CLKMGR_PERPLL_PLLC1,
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hoff_ptr->per_pll_pllc1);
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mmio_write_32(ALT_CLKMGR_PERPLL + ALT_CLKMGR_PERPLL_GPIODIV,
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ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_SET(
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hoff_ptr->per_pll_gpiodiv));
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mmio_write_32(ALT_CLKMGR_PERPLL + ALT_CLKMGR_PERPLL_EMACCTL,
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hoff_ptr->per_pll_emacctl);
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/* Take both PLL out of reset and power up */
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mmio_setbits_32(ALT_CLKMGR_MAINPLL + ALT_CLKMGR_MAINPLL_PLLGLOB,
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ALT_CLKMGR_MAINPLL_PLLGLOB_PD_SET_MSK |
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ALT_CLKMGR_MAINPLL_PLLGLOB_RST_SET_MSK);
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mmio_setbits_32(ALT_CLKMGR_PERPLL + ALT_CLKMGR_PERPLL_PLLGLOB,
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ALT_CLKMGR_PERPLL_PLLGLOB_PD_SET_MSK |
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ALT_CLKMGR_PERPLL_PLLGLOB_RST_SET_MSK);
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wait_pll_lock();
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/* Dividers for C2 to C9 only init after PLLs are lock. */
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mmio_write_32(ALT_CLKMGR_MAINPLL + ALT_CLKMGR_MAINPLL_MPUCLK, 0xff);
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mmio_write_32(ALT_CLKMGR_MAINPLL + ALT_CLKMGR_MAINPLL_NOCCLK, 0xff);
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mmio_write_32(ALT_CLKMGR_MAINPLL + ALT_CLKMGR_MAINPLL_CNTR2CLK, 0xff);
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mmio_write_32(ALT_CLKMGR_MAINPLL + ALT_CLKMGR_MAINPLL_CNTR3CLK, 0xff);
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mmio_write_32(ALT_CLKMGR_MAINPLL + ALT_CLKMGR_MAINPLL_CNTR4CLK, 0xff);
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mmio_write_32(ALT_CLKMGR_MAINPLL + ALT_CLKMGR_MAINPLL_CNTR5CLK, 0xff);
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mmio_write_32(ALT_CLKMGR_MAINPLL + ALT_CLKMGR_MAINPLL_CNTR6CLK, 0xff);
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mmio_write_32(ALT_CLKMGR_MAINPLL + ALT_CLKMGR_MAINPLL_CNTR7CLK, 0xff);
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mmio_write_32(ALT_CLKMGR_MAINPLL + ALT_CLKMGR_MAINPLL_CNTR8CLK, 0xff);
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mmio_write_32(ALT_CLKMGR_MAINPLL + ALT_CLKMGR_MAINPLL_CNTR9CLK, 0xff);
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mmio_write_32(ALT_CLKMGR_PERPLL + ALT_CLKMGR_PERPLL_CNTR2CLK, 0xff);
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mmio_write_32(ALT_CLKMGR_PERPLL + ALT_CLKMGR_PERPLL_CNTR3CLK, 0xff);
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mmio_write_32(ALT_CLKMGR_PERPLL + ALT_CLKMGR_PERPLL_CNTR4CLK, 0xff);
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mmio_write_32(ALT_CLKMGR_PERPLL + ALT_CLKMGR_PERPLL_CNTR5CLK, 0xff);
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mmio_write_32(ALT_CLKMGR_PERPLL + ALT_CLKMGR_PERPLL_CNTR6CLK, 0xff);
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mmio_write_32(ALT_CLKMGR_PERPLL + ALT_CLKMGR_PERPLL_CNTR7CLK, 0xff);
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mmio_write_32(ALT_CLKMGR_PERPLL + ALT_CLKMGR_PERPLL_CNTR8CLK, 0xff);
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mmio_write_32(ALT_CLKMGR_MAINPLL + ALT_CLKMGR_MAINPLL_MPUCLK,
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hoff_ptr->main_pll_mpuclk);
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mmio_write_32(ALT_CLKMGR_MAINPLL + ALT_CLKMGR_MAINPLL_NOCCLK,
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hoff_ptr->main_pll_nocclk);
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mmio_write_32(ALT_CLKMGR_MAINPLL + ALT_CLKMGR_MAINPLL_CNTR2CLK,
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hoff_ptr->main_pll_cntr2clk);
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mmio_write_32(ALT_CLKMGR_MAINPLL + ALT_CLKMGR_MAINPLL_CNTR3CLK,
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hoff_ptr->main_pll_cntr3clk);
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mmio_write_32(ALT_CLKMGR_MAINPLL + ALT_CLKMGR_MAINPLL_CNTR4CLK,
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hoff_ptr->main_pll_cntr4clk);
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mmio_write_32(ALT_CLKMGR_MAINPLL + ALT_CLKMGR_MAINPLL_CNTR5CLK,
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hoff_ptr->main_pll_cntr5clk);
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mmio_write_32(ALT_CLKMGR_MAINPLL + ALT_CLKMGR_MAINPLL_CNTR6CLK,
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hoff_ptr->main_pll_cntr6clk);
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mmio_write_32(ALT_CLKMGR_MAINPLL + ALT_CLKMGR_MAINPLL_CNTR7CLK,
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hoff_ptr->main_pll_cntr7clk);
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mmio_write_32(ALT_CLKMGR_MAINPLL + ALT_CLKMGR_MAINPLL_CNTR8CLK,
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hoff_ptr->main_pll_cntr8clk);
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mmio_write_32(ALT_CLKMGR_MAINPLL + ALT_CLKMGR_MAINPLL_CNTR9CLK,
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hoff_ptr->main_pll_cntr9clk);
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/* Peripheral PLL Clock Source and Counters/Divider */
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mmio_write_32(ALT_CLKMGR_PERPLL + ALT_CLKMGR_PERPLL_CNTR2CLK,
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hoff_ptr->per_pll_cntr2clk);
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mmio_write_32(ALT_CLKMGR_PERPLL + ALT_CLKMGR_PERPLL_CNTR3CLK,
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hoff_ptr->per_pll_cntr3clk);
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mmio_write_32(ALT_CLKMGR_PERPLL + ALT_CLKMGR_PERPLL_CNTR4CLK,
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hoff_ptr->per_pll_cntr4clk);
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mmio_write_32(ALT_CLKMGR_PERPLL + ALT_CLKMGR_PERPLL_CNTR5CLK,
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hoff_ptr->per_pll_cntr5clk);
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mmio_write_32(ALT_CLKMGR_PERPLL + ALT_CLKMGR_PERPLL_CNTR6CLK,
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hoff_ptr->per_pll_cntr6clk);
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mmio_write_32(ALT_CLKMGR_PERPLL + ALT_CLKMGR_PERPLL_CNTR7CLK,
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hoff_ptr->per_pll_cntr7clk);
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mmio_write_32(ALT_CLKMGR_PERPLL + ALT_CLKMGR_PERPLL_CNTR8CLK,
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hoff_ptr->per_pll_cntr8clk);
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mmio_write_32(ALT_CLKMGR_PERPLL + ALT_CLKMGR_PERPLL_CNTR9CLK,
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hoff_ptr->per_pll_cntr9clk);
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/* Take all PLLs out of bypass */
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mmio_write_32(ALT_CLKMGR_MAINPLL + ALT_CLKMGR_MAINPLL_BYPASS, 0);
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wait_fsm();
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mmio_write_32(ALT_CLKMGR_PERPLL + ALT_CLKMGR_PERPLL_BYPASS, 0);
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wait_fsm();
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/* Set safe mode/ out of boot mode */
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mmio_clrbits_32(ALT_CLKMGR + ALT_CLKMGR_CTRL,
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ALT_CLKMGR_CTRL_BOOTMODE_SET_MSK);
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wait_fsm();
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/* 10 Enable mainpllgrp's software-managed clock */
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mmio_write_32(ALT_CLKMGR_MAINPLL + ALT_CLKMGR_MAINPLL_EN,
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ALT_CLKMGR_MAINPLL_EN_RESET);
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mmio_write_32(ALT_CLKMGR_PERPLL + ALT_CLKMGR_PERPLL_EN,
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ALT_CLKMGR_PERPLL_EN_RESET);
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/* Clear loss lock interrupt status register that */
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/* might be set during configuration */
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mmio_write_32(ALT_CLKMGR + ALT_CLKMGR_INTRCLR,
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ALT_CLKMGR_INTRCLR_MAINLOCKLOST_SET_MSK |
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ALT_CLKMGR_INTRCLR_PERLOCKLOST_SET_MSK);
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}
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