82 lines
1.5 KiB
ArmAsm
82 lines
1.5 KiB
ArmAsm
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/*
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* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <assert_macros.S>
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#include <cortex_a15.h>
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#include <cpu_macros.S>
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/*
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* Cortex-A15 support LPAE and Virtualization Extensions.
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* Don't care if confiugration uses or not LPAE and VE.
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* Therefore, where we don't check ARCH_IS_ARMV7_WITH_LPAE/VE
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*/
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.macro assert_cache_enabled
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#if ENABLE_ASSERTIONS
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ldcopr r0, SCTLR
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tst r0, #SCTLR_C_BIT
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ASM_ASSERT(eq)
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#endif
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.endm
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func cortex_a15_disable_smp
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ldcopr r0, ACTLR
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bic r0, #CORTEX_A15_ACTLR_SMP_BIT
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stcopr r0, ACTLR
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isb
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dsb sy
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bx lr
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endfunc cortex_a15_disable_smp
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func cortex_a15_enable_smp
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ldcopr r0, ACTLR
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orr r0, #CORTEX_A15_ACTLR_SMP_BIT
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stcopr r0, ACTLR
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isb
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bx lr
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endfunc cortex_a15_enable_smp
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func cortex_a15_reset_func
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b cortex_a15_enable_smp
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endfunc cortex_a15_reset_func
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func cortex_a15_core_pwr_dwn
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push {r12, lr}
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assert_cache_enabled
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/* Flush L1 cache */
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mov r0, #DC_OP_CISW
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bl dcsw_op_level1
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/* Exit cluster coherency */
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pop {r12, lr}
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b cortex_a15_disable_smp
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endfunc cortex_a15_core_pwr_dwn
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func cortex_a15_cluster_pwr_dwn
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push {r12, lr}
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assert_cache_enabled
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/* Flush L1 caches */
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mov r0, #DC_OP_CISW
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bl dcsw_op_level1
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bl plat_disable_acp
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/* Exit cluster coherency */
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pop {r12, lr}
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b cortex_a15_disable_smp
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endfunc cortex_a15_cluster_pwr_dwn
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declare_cpu_ops cortex_a15, CORTEX_A15_MIDR, \
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cortex_a15_reset_func, \
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cortex_a15_core_pwr_dwn, \
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cortex_a15_cluster_pwr_dwn
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