2018-07-21 13:41:12 +01:00
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/*
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* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2018, Icenowy Zheng <icenowy@aosc.io>
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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2018-10-02 00:21:49 +01:00
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#include <errno.h>
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2018-12-14 00:18:21 +00:00
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2018-09-16 11:24:05 +01:00
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#include <libfdt.h>
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2018-12-14 00:18:21 +00:00
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2018-10-02 00:21:49 +01:00
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#include <platform_def.h>
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2018-12-14 00:18:21 +00:00
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#include <arch_helpers.h>
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#include <common/debug.h>
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#include <drivers/allwinner/sunxi_rsb.h>
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#include <drivers/delay_timer.h>
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#include <lib/mmio.h>
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2018-10-02 00:21:49 +01:00
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#include <sunxi_def.h>
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#include <sunxi_mmap.h>
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2018-10-14 12:02:02 +01:00
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#include <sunxi_private.h>
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2018-07-21 13:41:12 +01:00
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2018-10-02 00:21:49 +01:00
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static enum pmic_type {
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GENERIC_H5,
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GENERIC_A64,
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2018-10-02 00:21:53 +01:00
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REF_DESIGN_H5, /* regulators controlled by GPIO pins on port L */
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2018-09-15 01:18:49 +01:00
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AXP803_RSB, /* PMIC connected via RSB on most A64 boards */
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2018-10-02 00:21:49 +01:00
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} pmic;
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2018-09-15 01:18:49 +01:00
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#define AXP803_HW_ADDR 0x3a3
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#define AXP803_RT_ADDR 0x2d
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2018-10-02 00:21:49 +01:00
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/*
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* On boards without a proper PMIC we struggle to turn off the system properly.
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* Try to turn off as much off the system as we can, to reduce power
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* consumption. This should be entered with only one core running and SMP
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* disabled.
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* This function only cares about peripherals.
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*/
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void sunxi_turn_off_soc(uint16_t socid)
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2018-07-21 13:41:12 +01:00
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{
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2018-10-02 00:21:49 +01:00
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int i;
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/** Turn off most peripherals, most importantly DRAM users. **/
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/* Keep DRAM controller running for now. */
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mmio_clrbits_32(SUNXI_CCU_BASE + 0x2c0, ~BIT_32(14));
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mmio_clrbits_32(SUNXI_CCU_BASE + 0x60, ~BIT_32(14));
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/* Contains msgbox (bit 21) and spinlock (bit 22) */
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mmio_write_32(SUNXI_CCU_BASE + 0x2c4, 0);
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mmio_write_32(SUNXI_CCU_BASE + 0x64, 0);
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mmio_write_32(SUNXI_CCU_BASE + 0x2c8, 0);
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/* Keep PIO controller running for now. */
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mmio_clrbits_32(SUNXI_CCU_BASE + 0x68, ~(BIT_32(5)));
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mmio_write_32(SUNXI_CCU_BASE + 0x2d0, 0);
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/* Contains UART0 (bit 16) */
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mmio_write_32(SUNXI_CCU_BASE + 0x2d8, 0);
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mmio_write_32(SUNXI_CCU_BASE + 0x6c, 0);
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mmio_write_32(SUNXI_CCU_BASE + 0x70, 0);
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/** Turn off DRAM controller. **/
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mmio_clrbits_32(SUNXI_CCU_BASE + 0x2c0, BIT_32(14));
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mmio_clrbits_32(SUNXI_CCU_BASE + 0x60, BIT_32(14));
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2018-07-21 13:41:12 +01:00
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2018-10-02 00:21:49 +01:00
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/** Migrate CPU and bus clocks away from the PLLs. **/
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/* AHB1: use OSC24M/1, APB1 = AHB1 / 2 */
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mmio_write_32(SUNXI_CCU_BASE + 0x54, 0x1000);
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/* APB2: use OSC24M */
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mmio_write_32(SUNXI_CCU_BASE + 0x58, 0x1000000);
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/* AHB2: use AHB1 clock */
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mmio_write_32(SUNXI_CCU_BASE + 0x5c, 0);
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/* CPU: use OSC24M */
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mmio_write_32(SUNXI_CCU_BASE + 0x50, 0x10000);
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/** Turn off PLLs. **/
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for (i = 0; i < 6; i++)
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mmio_clrbits_32(SUNXI_CCU_BASE + i * 8, BIT(31));
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switch (socid) {
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case SUNXI_SOC_H5:
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mmio_clrbits_32(SUNXI_CCU_BASE + 0x44, BIT(31));
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break;
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case SUNXI_SOC_A64:
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mmio_clrbits_32(SUNXI_CCU_BASE + 0x2c, BIT(31));
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mmio_clrbits_32(SUNXI_CCU_BASE + 0x4c, BIT(31));
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break;
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}
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}
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2018-09-15 01:18:49 +01:00
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static int rsb_init(void)
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{
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int ret;
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ret = rsb_init_controller();
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if (ret)
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return ret;
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/* Start with 400 KHz to issue the I2C->RSB switch command. */
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ret = rsb_set_bus_speed(SUNXI_OSC24M_CLK_IN_HZ, 400000);
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if (ret)
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return ret;
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/*
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* Initiate an I2C transaction to write 0x7c into register 0x3e,
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* switching the PMIC to RSB mode.
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*/
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ret = rsb_set_device_mode(0x7c3e00);
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if (ret)
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return ret;
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/* Now in RSB mode, switch to the recommended 3 MHz. */
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ret = rsb_set_bus_speed(SUNXI_OSC24M_CLK_IN_HZ, 3000000);
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if (ret)
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return ret;
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/* Associate the 8-bit runtime address with the 12-bit bus address. */
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return rsb_assign_runtime_address(AXP803_HW_ADDR,
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AXP803_RT_ADDR);
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}
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allwinner: PMIC: AXP803: Setup basic voltage rails
Based on the just introduced PMIC FDT framework, we check the DT for more
voltage rails that need to be setup early:
- DCDC1 is typically the main board power rail, used for I/O pins, for
instance. The PMIC's default is 3.0V, but 3.3V is what most boards use,
so this needs to be adjusted as soon as possible.
- DCDC5 is supposed to be connected to the DRAM. The AXP has some
configurable reset voltage, but some boards get that wrong, so we better
set up this here to avoid over- or under-volting.
- DLDO1,2,3 and FLDO1 mostly drive some graphics related IP, some boards
need this to be up to enable HDMI or the LCD screen, so we get screen
output in U-Boot.
To get the right setup, but still being flexible, we query the DT for
the required voltage and whether that regulator is actually used. That
gives us some robust default setup U-Boot is happy with.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2018-09-16 11:24:34 +01:00
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static int axp_write(uint8_t reg, uint8_t val)
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{
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return rsb_write(AXP803_RT_ADDR, reg, val);
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}
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allwinner: power: fix DRIVEVBUS pin setup
The DRIVEVBUS pin setup was broken in two ways:
- To configure this pin as an output pin, one has to *clear* the bit in
register 0x8f. It is 0 by default, but rebooting from Linux might have
left this bit set.
- Doing this just configures the pin as an output pin, but doesn't
actually drive power to it. This is done via bit 2 in register 0x30.
Fix the routine to both properly configure the pin and drive power to
it. Add an axp_clrsetbits() helper on the way.
Now this isn't really perfect, still:
We only need to setup the PMIC power rails that are needed for U-Boot.
DRIVEVBUS typically controls the VBUS voltage for the host function of
an USB-OTG port, something we typically don't want in U-Boot (fastboot,
using the USB *device* functionality, is much more common). The
BananaPi-M64 uses the regulator in this way, but the Remix Mini PC
actually controls the power of both its USB ports via this line.
Technically we should differentiate here: if DRIVEVBUS controls a
microUSB-B socket, the power should stay off, any host-type A sockets
should be supplied, though.
For now just always enable the power, that shouldn't really hurt the
USB-OTG functionality anyway.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2018-11-05 00:52:06 +00:00
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static int axp_clrsetbits(uint8_t reg, uint8_t clr_mask, uint8_t set_mask)
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2018-09-15 01:18:49 +01:00
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{
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uint8_t regval;
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int ret;
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ret = rsb_read(AXP803_RT_ADDR, reg);
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if (ret < 0)
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return ret;
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allwinner: power: fix DRIVEVBUS pin setup
The DRIVEVBUS pin setup was broken in two ways:
- To configure this pin as an output pin, one has to *clear* the bit in
register 0x8f. It is 0 by default, but rebooting from Linux might have
left this bit set.
- Doing this just configures the pin as an output pin, but doesn't
actually drive power to it. This is done via bit 2 in register 0x30.
Fix the routine to both properly configure the pin and drive power to
it. Add an axp_clrsetbits() helper on the way.
Now this isn't really perfect, still:
We only need to setup the PMIC power rails that are needed for U-Boot.
DRIVEVBUS typically controls the VBUS voltage for the host function of
an USB-OTG port, something we typically don't want in U-Boot (fastboot,
using the USB *device* functionality, is much more common). The
BananaPi-M64 uses the regulator in this way, but the Remix Mini PC
actually controls the power of both its USB ports via this line.
Technically we should differentiate here: if DRIVEVBUS controls a
microUSB-B socket, the power should stay off, any host-type A sockets
should be supplied, though.
For now just always enable the power, that shouldn't really hurt the
USB-OTG functionality anyway.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2018-11-05 00:52:06 +00:00
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regval = (ret & ~clr_mask) | set_mask;
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2018-09-15 01:18:49 +01:00
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return rsb_write(AXP803_RT_ADDR, reg, regval);
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}
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allwinner: power: fix DRIVEVBUS pin setup
The DRIVEVBUS pin setup was broken in two ways:
- To configure this pin as an output pin, one has to *clear* the bit in
register 0x8f. It is 0 by default, but rebooting from Linux might have
left this bit set.
- Doing this just configures the pin as an output pin, but doesn't
actually drive power to it. This is done via bit 2 in register 0x30.
Fix the routine to both properly configure the pin and drive power to
it. Add an axp_clrsetbits() helper on the way.
Now this isn't really perfect, still:
We only need to setup the PMIC power rails that are needed for U-Boot.
DRIVEVBUS typically controls the VBUS voltage for the host function of
an USB-OTG port, something we typically don't want in U-Boot (fastboot,
using the USB *device* functionality, is much more common). The
BananaPi-M64 uses the regulator in this way, but the Remix Mini PC
actually controls the power of both its USB ports via this line.
Technically we should differentiate here: if DRIVEVBUS controls a
microUSB-B socket, the power should stay off, any host-type A sockets
should be supplied, though.
For now just always enable the power, that shouldn't really hurt the
USB-OTG functionality anyway.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2018-11-05 00:52:06 +00:00
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#define axp_clrbits(reg, clr_mask) axp_clrsetbits(reg, clr_mask, 0)
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#define axp_setbits(reg, set_mask) axp_clrsetbits(reg, 0, set_mask)
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2018-09-16 11:24:05 +01:00
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static bool should_enable_regulator(const void *fdt, int node)
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{
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if (fdt_getprop(fdt, node, "phandle", NULL) != NULL)
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return true;
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if (fdt_getprop(fdt, node, "regulator-always-on", NULL) != NULL)
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return true;
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return false;
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}
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allwinner: PMIC: AXP803: Setup basic voltage rails
Based on the just introduced PMIC FDT framework, we check the DT for more
voltage rails that need to be setup early:
- DCDC1 is typically the main board power rail, used for I/O pins, for
instance. The PMIC's default is 3.0V, but 3.3V is what most boards use,
so this needs to be adjusted as soon as possible.
- DCDC5 is supposed to be connected to the DRAM. The AXP has some
configurable reset voltage, but some boards get that wrong, so we better
set up this here to avoid over- or under-volting.
- DLDO1,2,3 and FLDO1 mostly drive some graphics related IP, some boards
need this to be up to enable HDMI or the LCD screen, so we get screen
output in U-Boot.
To get the right setup, but still being flexible, we query the DT for
the required voltage and whether that regulator is actually used. That
gives us some robust default setup U-Boot is happy with.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2018-09-16 11:24:34 +01:00
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/*
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* Retrieve the voltage from a given regulator DTB node.
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* Both the regulator-{min,max}-microvolt properties must be present and
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* have the same value. Return that value in millivolts.
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*/
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static int fdt_get_regulator_millivolt(const void *fdt, int node)
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{
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const fdt32_t *prop;
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uint32_t min_volt;
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prop = fdt_getprop(fdt, node, "regulator-min-microvolt", NULL);
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if (prop == NULL)
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return -EINVAL;
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min_volt = fdt32_to_cpu(*prop);
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prop = fdt_getprop(fdt, node, "regulator-max-microvolt", NULL);
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if (prop == NULL)
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return -EINVAL;
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if (fdt32_to_cpu(*prop) != min_volt)
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return -EINVAL;
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return min_volt / 1000;
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}
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#define NO_SPLIT 0xff
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2019-02-17 21:09:11 +00:00
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static const struct axp_regulator {
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allwinner: PMIC: AXP803: Setup basic voltage rails
Based on the just introduced PMIC FDT framework, we check the DT for more
voltage rails that need to be setup early:
- DCDC1 is typically the main board power rail, used for I/O pins, for
instance. The PMIC's default is 3.0V, but 3.3V is what most boards use,
so this needs to be adjusted as soon as possible.
- DCDC5 is supposed to be connected to the DRAM. The AXP has some
configurable reset voltage, but some boards get that wrong, so we better
set up this here to avoid over- or under-volting.
- DLDO1,2,3 and FLDO1 mostly drive some graphics related IP, some boards
need this to be up to enable HDMI or the LCD screen, so we get screen
output in U-Boot.
To get the right setup, but still being flexible, we query the DT for
the required voltage and whether that regulator is actually used. That
gives us some robust default setup U-Boot is happy with.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2018-09-16 11:24:34 +01:00
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char *dt_name;
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uint16_t min_volt;
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uint16_t max_volt;
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uint16_t step;
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unsigned char split;
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unsigned char volt_reg;
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unsigned char switch_reg;
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unsigned char switch_bit;
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} regulators[] = {
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2018-10-24 16:38:12 +01:00
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{"dcdc1", 1600, 3400, 100, NO_SPLIT, 0x20, 0x10, 0},
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{"dcdc5", 800, 1840, 10, 32, 0x24, 0x10, 4},
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2018-10-24 16:38:19 +01:00
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{"dcdc6", 600, 1520, 10, 50, 0x25, 0x10, 5},
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allwinner: PMIC: AXP803: Setup basic voltage rails
Based on the just introduced PMIC FDT framework, we check the DT for more
voltage rails that need to be setup early:
- DCDC1 is typically the main board power rail, used for I/O pins, for
instance. The PMIC's default is 3.0V, but 3.3V is what most boards use,
so this needs to be adjusted as soon as possible.
- DCDC5 is supposed to be connected to the DRAM. The AXP has some
configurable reset voltage, but some boards get that wrong, so we better
set up this here to avoid over- or under-volting.
- DLDO1,2,3 and FLDO1 mostly drive some graphics related IP, some boards
need this to be up to enable HDMI or the LCD screen, so we get screen
output in U-Boot.
To get the right setup, but still being flexible, we query the DT for
the required voltage and whether that regulator is actually used. That
gives us some robust default setup U-Boot is happy with.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2018-09-16 11:24:34 +01:00
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{"dldo1", 700, 3300, 100, NO_SPLIT, 0x15, 0x12, 3},
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{"dldo2", 700, 4200, 100, 27, 0x16, 0x12, 4},
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{"dldo3", 700, 3300, 100, NO_SPLIT, 0x17, 0x12, 5},
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{"fldo1", 700, 1450, 50, NO_SPLIT, 0x1c, 0x13, 2},
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{}
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};
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static int setup_regulator(const void *fdt, int node,
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const struct axp_regulator *reg)
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{
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int mvolt;
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uint8_t regval;
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if (!should_enable_regulator(fdt, node))
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return -ENOENT;
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mvolt = fdt_get_regulator_millivolt(fdt, node);
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if (mvolt < reg->min_volt || mvolt > reg->max_volt)
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return -EINVAL;
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regval = (mvolt / reg->step) - (reg->min_volt / reg->step);
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if (regval > reg->split)
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regval = ((regval - reg->split) / 2) + reg->split;
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axp_write(reg->volt_reg, regval);
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if (reg->switch_reg < 0xff)
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axp_setbits(reg->switch_reg, BIT(reg->switch_bit));
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INFO("PMIC: AXP803: %s voltage: %d.%03dV\n", reg->dt_name,
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mvolt / 1000, mvolt % 1000);
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return 0;
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}
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2018-09-16 11:24:05 +01:00
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static void setup_axp803_rails(const void *fdt)
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|
|
|
{
|
|
|
|
int node;
|
2018-09-19 21:17:00 +01:00
|
|
|
bool dc1sw = false;
|
2018-09-16 11:24:05 +01:00
|
|
|
|
|
|
|
/* locate the PMIC DT node, bail out if not found */
|
|
|
|
node = fdt_node_offset_by_compatible(fdt, -1, "x-powers,axp803");
|
2019-02-17 22:10:11 +00:00
|
|
|
if (node < 0) {
|
|
|
|
WARN("BL31: PMIC: Cannot find AXP803 DT node, skipping initial setup.\n");
|
2018-09-16 11:24:05 +01:00
|
|
|
return;
|
|
|
|
}
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|
|
|
|
allwinner: power: fix DRIVEVBUS pin setup
The DRIVEVBUS pin setup was broken in two ways:
- To configure this pin as an output pin, one has to *clear* the bit in
register 0x8f. It is 0 by default, but rebooting from Linux might have
left this bit set.
- Doing this just configures the pin as an output pin, but doesn't
actually drive power to it. This is done via bit 2 in register 0x30.
Fix the routine to both properly configure the pin and drive power to
it. Add an axp_clrsetbits() helper on the way.
Now this isn't really perfect, still:
We only need to setup the PMIC power rails that are needed for U-Boot.
DRIVEVBUS typically controls the VBUS voltage for the host function of
an USB-OTG port, something we typically don't want in U-Boot (fastboot,
using the USB *device* functionality, is much more common). The
BananaPi-M64 uses the regulator in this way, but the Remix Mini PC
actually controls the power of both its USB ports via this line.
Technically we should differentiate here: if DRIVEVBUS controls a
microUSB-B socket, the power should stay off, any host-type A sockets
should be supplied, though.
For now just always enable the power, that shouldn't really hurt the
USB-OTG functionality anyway.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2018-11-05 00:52:06 +00:00
|
|
|
if (fdt_getprop(fdt, node, "x-powers,drive-vbus-en", NULL)) {
|
|
|
|
axp_clrbits(0x8f, BIT(4));
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|
|
|
axp_setbits(0x30, BIT(2));
|
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|
|
INFO("PMIC: AXP803: Enabling DRIVEVBUS\n");
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|
|
}
|
2018-09-16 11:24:05 +01:00
|
|
|
|
|
|
|
/* descend into the "regulators" subnode */
|
2019-02-17 22:10:11 +00:00
|
|
|
node = fdt_subnode_offset(fdt, node, "regulators");
|
|
|
|
if (node < 0) {
|
|
|
|
WARN("BL31: PMIC: Cannot find regulators subnode, skipping initial setup.\n");
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|
|
|
return;
|
|
|
|
}
|
2018-09-16 11:24:05 +01:00
|
|
|
|
|
|
|
/* iterate over all regulators to find used ones */
|
|
|
|
for (node = fdt_first_subnode(fdt, node);
|
2019-02-17 22:10:11 +00:00
|
|
|
node >= 0;
|
2018-09-16 11:24:05 +01:00
|
|
|
node = fdt_next_subnode(fdt, node)) {
|
2019-02-17 21:09:11 +00:00
|
|
|
const struct axp_regulator *reg;
|
2018-09-16 11:24:05 +01:00
|
|
|
const char *name;
|
|
|
|
int length;
|
|
|
|
|
|
|
|
/* We only care if it's always on or referenced. */
|
|
|
|
if (!should_enable_regulator(fdt, node))
|
|
|
|
continue;
|
|
|
|
|
|
|
|
name = fdt_get_name(fdt, node, &length);
|
allwinner: PMIC: AXP803: Setup basic voltage rails
Based on the just introduced PMIC FDT framework, we check the DT for more
voltage rails that need to be setup early:
- DCDC1 is typically the main board power rail, used for I/O pins, for
instance. The PMIC's default is 3.0V, but 3.3V is what most boards use,
so this needs to be adjusted as soon as possible.
- DCDC5 is supposed to be connected to the DRAM. The AXP has some
configurable reset voltage, but some boards get that wrong, so we better
set up this here to avoid over- or under-volting.
- DLDO1,2,3 and FLDO1 mostly drive some graphics related IP, some boards
need this to be up to enable HDMI or the LCD screen, so we get screen
output in U-Boot.
To get the right setup, but still being flexible, we query the DT for
the required voltage and whether that regulator is actually used. That
gives us some robust default setup U-Boot is happy with.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2018-09-16 11:24:34 +01:00
|
|
|
for (reg = regulators; reg->dt_name; reg++) {
|
|
|
|
if (!strncmp(name, reg->dt_name, length)) {
|
|
|
|
setup_regulator(fdt, node, reg);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2018-09-16 11:24:05 +01:00
|
|
|
if (!strncmp(name, "dc1sw", length)) {
|
2018-09-19 21:17:00 +01:00
|
|
|
/* Delay DC1SW enablement to avoid overheating. */
|
|
|
|
dc1sw = true;
|
2018-09-16 11:24:05 +01:00
|
|
|
continue;
|
|
|
|
}
|
|
|
|
}
|
2018-09-19 21:17:00 +01:00
|
|
|
/*
|
|
|
|
* If DLDO2 is enabled after DC1SW, the PMIC overheats and shuts
|
|
|
|
* down. So always enable DC1SW as the very last regulator.
|
|
|
|
*/
|
|
|
|
if (dc1sw) {
|
|
|
|
INFO("PMIC: AXP803: Enabling DC1SW\n");
|
|
|
|
axp_setbits(0x12, BIT(7));
|
|
|
|
}
|
2018-09-16 11:24:05 +01:00
|
|
|
}
|
|
|
|
|
2018-09-08 19:18:37 +01:00
|
|
|
int sunxi_pmic_setup(uint16_t socid, const void *fdt)
|
2018-10-02 00:21:49 +01:00
|
|
|
{
|
2018-09-15 01:18:49 +01:00
|
|
|
int ret;
|
|
|
|
|
2018-10-02 00:21:49 +01:00
|
|
|
switch (socid) {
|
|
|
|
case SUNXI_SOC_H5:
|
2018-10-02 00:21:53 +01:00
|
|
|
pmic = REF_DESIGN_H5;
|
|
|
|
NOTICE("BL31: PMIC: Defaulting to PortL GPIO according to H5 reference design.\n");
|
2018-10-02 00:21:49 +01:00
|
|
|
break;
|
|
|
|
case SUNXI_SOC_A64:
|
|
|
|
pmic = GENERIC_A64;
|
2018-09-15 01:18:49 +01:00
|
|
|
ret = sunxi_init_platform_r_twi(socid, true);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
ret = rsb_init();
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
pmic = AXP803_RSB;
|
|
|
|
NOTICE("BL31: PMIC: Detected AXP803 on RSB.\n");
|
|
|
|
|
2018-09-16 11:24:05 +01:00
|
|
|
if (fdt)
|
|
|
|
setup_axp803_rails(fdt);
|
|
|
|
|
2018-10-02 00:21:49 +01:00
|
|
|
break;
|
|
|
|
default:
|
|
|
|
NOTICE("BL31: PMIC: No support for Allwinner %x SoC.\n", socid);
|
|
|
|
return -ENODEV;
|
|
|
|
}
|
2018-07-21 13:41:12 +01:00
|
|
|
return 0;
|
|
|
|
}
|
2018-07-22 14:52:50 +01:00
|
|
|
|
|
|
|
void __dead2 sunxi_power_down(void)
|
|
|
|
{
|
2018-10-02 00:21:49 +01:00
|
|
|
switch (pmic) {
|
|
|
|
case GENERIC_H5:
|
|
|
|
/* Turn off as many peripherals and clocks as we can. */
|
|
|
|
sunxi_turn_off_soc(SUNXI_SOC_H5);
|
|
|
|
/* Turn off the pin controller now. */
|
|
|
|
mmio_write_32(SUNXI_CCU_BASE + 0x68, 0);
|
|
|
|
break;
|
|
|
|
case GENERIC_A64:
|
|
|
|
/* Turn off as many peripherals and clocks as we can. */
|
|
|
|
sunxi_turn_off_soc(SUNXI_SOC_A64);
|
|
|
|
/* Turn off the pin controller now. */
|
|
|
|
mmio_write_32(SUNXI_CCU_BASE + 0x68, 0);
|
2018-10-02 00:21:53 +01:00
|
|
|
break;
|
|
|
|
case REF_DESIGN_H5:
|
|
|
|
sunxi_turn_off_soc(SUNXI_SOC_H5);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Switch PL pins to power off the board:
|
|
|
|
* - PL5 (VCC_IO) -> high
|
|
|
|
* - PL8 (PWR-STB = CPU power supply) -> low
|
|
|
|
* - PL9 (PWR-DRAM) ->low
|
|
|
|
* - PL10 (power LED) -> low
|
|
|
|
* Note: Clearing PL8 will reset the board, so keep it up.
|
|
|
|
*/
|
|
|
|
sunxi_set_gpio_out('L', 5, 1);
|
|
|
|
sunxi_set_gpio_out('L', 9, 0);
|
|
|
|
sunxi_set_gpio_out('L', 10, 0);
|
|
|
|
|
|
|
|
/* Turn off pin controller now. */
|
|
|
|
mmio_write_32(SUNXI_CCU_BASE + 0x68, 0);
|
|
|
|
|
2018-09-15 01:18:49 +01:00
|
|
|
break;
|
|
|
|
case AXP803_RSB:
|
|
|
|
/* (Re-)init RSB in case the rich OS has disabled it. */
|
|
|
|
sunxi_init_platform_r_twi(SUNXI_SOC_A64, true);
|
|
|
|
rsb_init();
|
|
|
|
|
|
|
|
/* Set "power disable control" bit */
|
|
|
|
axp_setbits(0x32, BIT(7));
|
2018-10-02 00:21:49 +01:00
|
|
|
break;
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
udelay(1000);
|
|
|
|
ERROR("PSCI: Cannot turn off system, halting.\n");
|
2018-07-22 14:52:50 +01:00
|
|
|
wfi();
|
|
|
|
panic();
|
|
|
|
}
|