2017-02-24 08:26:11 +00:00
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/*
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* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
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*
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2017-05-03 09:38:09 +01:00
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* SPDX-License-Identifier: BSD-3-Clause
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2017-02-24 08:26:11 +00:00
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*/
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2018-11-08 10:20:19 +00:00
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#ifndef MISC_REGS_H
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#define MISC_REGS_H
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2017-02-24 08:26:11 +00:00
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/* CRU */
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#define CRU_DPLL_CON0 0x40
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#define CRU_DPLL_CON1 0x44
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#define CRU_DPLL_CON2 0x48
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#define CRU_DPLL_CON3 0x4c
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#define CRU_DPLL_CON4 0x50
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#define CRU_DPLL_CON5 0x54
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/* CRU_PLL_CON3 */
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#define PLL_SLOW_MODE 0
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#define PLL_NORMAL_MODE 1
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#define PLL_MODE(n) ((0x3 << (8 + 16)) | ((n) << 8))
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#define PLL_POWER_DOWN(n) ((0x1 << (0 + 16)) | ((n) << 0))
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/* PMU CRU */
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#define PMU_CRU_GATEDIS_CON0 0x130
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2018-11-08 10:20:19 +00:00
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#endif /* MISC_REGS_H */
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