2015-06-29 16:30:12 +01:00
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/*
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2015-05-05 16:33:16 +01:00
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* Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved.
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2015-06-29 16:30:12 +01:00
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <arch.h>
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#include <arch_helpers.h>
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#include <assert.h>
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#include <bl_common.h>
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#include <context.h>
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#include <context_mgmt.h>
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#include <platform.h>
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#include <stddef.h>
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#include "psci_private.h"
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/*******************************************************************************
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* Per cpu non-secure contexts used to program the architectural state prior
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* return to the normal world.
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* TODO: Use the memory allocator to set aside memory for the contexts instead
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2015-04-08 17:42:06 +01:00
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* of relying on platform defined constants.
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2015-06-29 16:30:12 +01:00
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******************************************************************************/
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static cpu_context_t psci_ns_context[PLATFORM_CORE_COUNT];
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/******************************************************************************
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* Define the psci capability variable.
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*****************************************************************************/
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uint32_t psci_caps;
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/*******************************************************************************
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2015-04-08 17:42:06 +01:00
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* Function which initializes the 'psci_non_cpu_pd_nodes' or the
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* 'psci_cpu_pd_nodes' corresponding to the power level.
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2015-06-29 16:30:12 +01:00
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******************************************************************************/
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2015-04-08 17:42:06 +01:00
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static void psci_init_pwr_domain_node(int node_idx, int parent_idx, int level)
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2015-06-29 16:30:12 +01:00
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{
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2015-04-08 17:42:06 +01:00
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if (level > PSCI_CPU_PWR_LVL) {
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psci_non_cpu_pd_nodes[node_idx].level = level;
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psci_lock_init(psci_non_cpu_pd_nodes, node_idx);
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psci_non_cpu_pd_nodes[node_idx].parent_node = parent_idx;
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} else {
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2015-06-29 16:30:12 +01:00
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2015-04-08 17:42:06 +01:00
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psci_cpu_pd_nodes[node_idx].parent_node = parent_idx;
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2015-06-29 16:30:12 +01:00
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2015-04-08 17:42:06 +01:00
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/* Initialize with an invalid mpidr */
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psci_cpu_pd_nodes[node_idx].mpidr = PSCI_INVALID_MPIDR;
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2015-06-29 16:30:12 +01:00
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/*
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2015-04-08 17:42:06 +01:00
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* Mark the cpu as OFF.
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2015-06-29 16:30:12 +01:00
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*/
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2015-04-08 17:42:06 +01:00
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set_cpu_data_by_index(node_idx,
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psci_svc_cpu_data.psci_state,
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PSCI_STATE_OFF);
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2015-06-29 16:30:12 +01:00
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2015-04-08 17:42:06 +01:00
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/* Invalidate the suspend context for the node */
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set_cpu_data_by_index(node_idx,
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psci_svc_cpu_data.power_state,
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PSCI_INVALID_DATA);
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2015-06-29 16:30:12 +01:00
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2015-04-08 17:42:06 +01:00
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flush_cpu_data_by_index(node_idx, psci_svc_cpu_data);
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2015-06-29 16:30:12 +01:00
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2015-04-08 17:42:06 +01:00
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cm_set_context_by_index(node_idx,
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(void *) &psci_ns_context[node_idx],
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NON_SECURE);
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}
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2015-06-29 16:30:12 +01:00
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}
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/*******************************************************************************
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2015-04-08 17:42:06 +01:00
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* This functions updates cpu_start_idx and ncpus field for each of the node in
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* psci_non_cpu_pd_nodes[]. It does so by comparing the parent nodes of each of
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* the CPUs and check whether they match with the parent of the previous
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* CPU. The basic assumption for this work is that children of the same parent
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* are allocated adjacent indices. The platform should ensure this though proper
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* mapping of the CPUs to indices via plat_core_pos_by_mpidr() and
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* plat_my_core_pos() APIs.
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*******************************************************************************/
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static void psci_update_pwrlvl_limits(void)
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2015-06-29 16:30:12 +01:00
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{
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2015-04-08 17:42:06 +01:00
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int cpu_idx, j;
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unsigned int nodes_idx[PLAT_MAX_PWR_LVL] = {0};
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unsigned int temp_index[PLAT_MAX_PWR_LVL];
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for (cpu_idx = 0; cpu_idx < PLATFORM_CORE_COUNT; cpu_idx++) {
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psci_get_parent_pwr_domain_nodes(cpu_idx,
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PLAT_MAX_PWR_LVL,
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temp_index);
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for (j = PLAT_MAX_PWR_LVL - 1; j >= 0; j--) {
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if (temp_index[j] != nodes_idx[j]) {
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nodes_idx[j] = temp_index[j];
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psci_non_cpu_pd_nodes[nodes_idx[j]].cpu_start_idx
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= cpu_idx;
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}
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psci_non_cpu_pd_nodes[nodes_idx[j]].ncpus++;
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}
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}
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2015-06-29 16:30:12 +01:00
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}
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/*******************************************************************************
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2015-04-08 17:42:06 +01:00
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* Core routine to populate the power domain tree. The tree descriptor passed by
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* the platform is populated breadth-first and the first entry in the map
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* informs the number of root power domains. The parent nodes of the root nodes
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* will point to an invalid entry(-1).
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2015-06-29 16:30:12 +01:00
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******************************************************************************/
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2015-04-08 17:42:06 +01:00
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static void populate_power_domain_tree(const unsigned char *topology)
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2015-06-29 16:30:12 +01:00
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{
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2015-04-08 17:42:06 +01:00
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unsigned int i, j = 0, num_nodes_at_lvl = 1, num_nodes_at_next_lvl;
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unsigned int node_index = 0, parent_node_index = 0, num_children;
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int level = PLAT_MAX_PWR_LVL;
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2015-06-29 16:30:12 +01:00
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/*
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2015-04-08 17:42:06 +01:00
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* For each level the inputs are:
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* - number of nodes at this level in plat_array i.e. num_nodes_at_level
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* This is the sum of values of nodes at the parent level.
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* - Index of first entry at this level in the plat_array i.e.
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* parent_node_index.
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* - Index of first free entry in psci_non_cpu_pd_nodes[] or
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* psci_cpu_pd_nodes[] i.e. node_index depending upon the level.
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2015-06-29 16:30:12 +01:00
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*/
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2015-04-08 17:42:06 +01:00
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while (level >= PSCI_CPU_PWR_LVL) {
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num_nodes_at_next_lvl = 0;
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/*
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* For each entry (parent node) at this level in the plat_array:
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* - Find the number of children
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* - Allocate a node in a power domain array for each child
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* - Set the parent of the child to the parent_node_index - 1
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* - Increment parent_node_index to point to the next parent
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* - Accumulate the number of children at next level.
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*/
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for (i = 0; i < num_nodes_at_lvl; i++) {
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assert(parent_node_index <=
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PSCI_NUM_NON_CPU_PWR_DOMAINS);
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num_children = topology[parent_node_index];
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for (j = node_index;
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j < node_index + num_children; j++)
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psci_init_pwr_domain_node(j,
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parent_node_index - 1,
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level);
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node_index = j;
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num_nodes_at_next_lvl += num_children;
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parent_node_index++;
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2015-06-29 16:30:12 +01:00
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}
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2015-04-08 17:42:06 +01:00
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num_nodes_at_lvl = num_nodes_at_next_lvl;
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level--;
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/* Reset the index for the cpu power domain array */
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if (level == PSCI_CPU_PWR_LVL)
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node_index = 0;
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2015-06-29 16:30:12 +01:00
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}
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2015-04-08 17:42:06 +01:00
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/* Validate the sanity of array exported by the platform */
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assert(j == PLATFORM_CORE_COUNT);
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#if !USE_COHERENT_MEM
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/* Flush the non CPU power domain data to memory */
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flush_dcache_range((uint64_t) &psci_non_cpu_pd_nodes,
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sizeof(psci_non_cpu_pd_nodes));
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#endif
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2015-06-29 16:30:12 +01:00
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}
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/*******************************************************************************
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2015-04-08 17:42:06 +01:00
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* This function initializes the power domain topology tree by querying the
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* platform. The power domain nodes higher than the CPU are populated in the
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* array psci_non_cpu_pd_nodes[] and the CPU power domains are populated in
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* psci_cpu_pd_nodes[]. The platform exports its static topology map through the
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* populate_power_domain_topology_tree() API. The algorithm populates the
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* psci_non_cpu_pd_nodes and psci_cpu_pd_nodes iteratively by using this
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* topology map. On a platform that implements two clusters of 2 cpus each, and
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* supporting 3 domain levels, the populated psci_non_cpu_pd_nodes would look
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* like this:
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2015-06-29 16:30:12 +01:00
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*
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* ---------------------------------------------------
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2015-04-08 17:42:06 +01:00
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* | system node | cluster 0 node | cluster 1 node |
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2015-06-29 16:30:12 +01:00
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* ---------------------------------------------------
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*
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2015-04-08 17:42:06 +01:00
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* And populated psci_cpu_pd_nodes would look like this :
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* <- cpus cluster0 -><- cpus cluster1 ->
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* ------------------------------------------------
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* | CPU 0 | CPU 1 | CPU 2 | CPU 3 |
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* ------------------------------------------------
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2015-06-29 16:30:12 +01:00
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******************************************************************************/
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int32_t psci_setup(void)
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{
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2015-04-08 17:42:06 +01:00
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const unsigned char *topology_tree;
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2015-06-29 16:30:12 +01:00
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2015-04-08 17:42:06 +01:00
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/* Query the topology map from the platform */
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topology_tree = plat_get_power_domain_tree_desc();
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2015-06-29 16:30:12 +01:00
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2015-04-08 17:42:06 +01:00
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/* Populate the power domain arrays using the platform topology map */
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populate_power_domain_tree(topology_tree);
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2015-06-29 16:30:12 +01:00
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2015-04-08 17:42:06 +01:00
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/* Update the CPU limits for each node in psci_non_cpu_pd_nodes */
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psci_update_pwrlvl_limits();
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/* Populate the mpidr field of cpu node for this CPU */
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psci_cpu_pd_nodes[plat_my_core_pos()].mpidr =
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read_mpidr() & MPIDR_AFFINITY_MASK;
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2015-06-29 16:30:12 +01:00
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#if !USE_COHERENT_MEM
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/*
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2015-04-08 17:42:06 +01:00
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* The psci_non_cpu_pd_nodes only needs flushing when it's not allocated in
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* coherent memory.
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2015-06-29 16:30:12 +01:00
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*/
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2015-04-08 17:42:06 +01:00
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flush_dcache_range((uint64_t) &psci_non_cpu_pd_nodes,
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sizeof(psci_non_cpu_pd_nodes));
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2015-06-29 16:30:12 +01:00
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#endif
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2015-04-08 17:42:06 +01:00
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flush_dcache_range((uint64_t) &psci_cpu_pd_nodes,
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sizeof(psci_cpu_pd_nodes));
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2015-06-29 16:30:12 +01:00
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/*
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2015-04-08 17:42:06 +01:00
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* Mark the current CPU and its parent power domains as ON. No need to lock
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* as the system is UP on the primary at this stage of boot.
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2015-06-29 16:30:12 +01:00
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*/
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2015-04-08 17:42:06 +01:00
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psci_do_state_coordination(PLAT_MAX_PWR_LVL, plat_my_core_pos(),
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PSCI_STATE_ON);
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2015-06-29 16:30:12 +01:00
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platform_setup_pm(&psci_plat_pm_ops);
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assert(psci_plat_pm_ops);
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/* Initialize the psci capability */
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psci_caps = PSCI_GENERIC_CAP;
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2015-05-05 16:33:16 +01:00
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if (psci_plat_pm_ops->pwr_domain_off)
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2015-06-29 16:30:12 +01:00
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psci_caps |= define_psci_cap(PSCI_CPU_OFF);
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2015-05-05 16:33:16 +01:00
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if (psci_plat_pm_ops->pwr_domain_on &&
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psci_plat_pm_ops->pwr_domain_on_finish)
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2015-06-29 16:30:12 +01:00
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psci_caps |= define_psci_cap(PSCI_CPU_ON_AARCH64);
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2015-05-05 16:33:16 +01:00
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if (psci_plat_pm_ops->pwr_domain_suspend &&
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psci_plat_pm_ops->pwr_domain_suspend_finish) {
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2015-06-29 16:30:12 +01:00
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psci_caps |= define_psci_cap(PSCI_CPU_SUSPEND_AARCH64);
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if (psci_plat_pm_ops->get_sys_suspend_power_state)
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psci_caps |= define_psci_cap(PSCI_SYSTEM_SUSPEND_AARCH64);
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}
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if (psci_plat_pm_ops->system_off)
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psci_caps |= define_psci_cap(PSCI_SYSTEM_OFF);
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if (psci_plat_pm_ops->system_reset)
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psci_caps |= define_psci_cap(PSCI_SYSTEM_RESET);
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return 0;
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}
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