2016-01-28 17:22:16 +00:00
|
|
|
/*
|
Increase type widths to satisfy width requirements
Usually, C has no problem up-converting types to larger bit sizes. MISRA
rule 10.7 requires that you not do this, or be very explicit about this.
This resolves the following required rule:
bl1/aarch64/bl1_context_mgmt.c:81:[MISRA C-2012 Rule 10.7 (required)]<None>
The width of the composite expression "0U | ((mode & 3U) << 2U) | 1U |
0x3c0U" (32 bits) is less that the right hand operand
"18446744073709547519ULL" (64 bits).
This also resolves MISRA defects such as:
bl2/aarch64/bl2arch_setup.c:18:[MISRA C-2012 Rule 12.2 (required)]
In the expression "3U << 20", shifting more than 7 bits, the number
of bits in the essential type of the left expression, "3U", is
not allowed.
Further, MISRA requires that all shifts don't overflow. The definition of
PAGE_SIZE was (1U << 12), and 1U is 8 bits. This caused about 50 issues.
This fixes the violation by changing the definition to 1UL << 12. Since
this uses 32bits, it should not create any issues for aarch32.
This patch also contains a fix for a build failure in the sun50i_a64
platform. Specifically, these misra fixes removed a single and
instruction,
92407e73 and x19, x19, #0xffffffff
from the cm_setup_context function caused a relocation in
psci_cpus_on_start to require a linker-generated stub. This increased the
size of the .text section and caused an alignment later on to go over a
page boundary and round up to the end of RAM before placing the .data
section. This sectionn is of non-zero size and therefore causes a link
error.
The fix included in this reorders the functions during link time
without changing their ording with respect to alignment.
Change-Id: I76b4b662c3d262296728a8b9aab7a33b02087f16
Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>
2020-08-04 22:18:52 +01:00
|
|
|
* Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved.
|
2016-01-28 17:22:16 +00:00
|
|
|
*
|
2017-05-03 09:38:09 +01:00
|
|
|
* SPDX-License-Identifier: BSD-3-Clause
|
2016-01-28 17:22:16 +00:00
|
|
|
*/
|
|
|
|
|
2018-10-15 14:58:11 +01:00
|
|
|
#ifndef TZC_COMMON_PRIVATE_H
|
|
|
|
#define TZC_COMMON_PRIVATE_H
|
2017-02-28 10:58:25 +00:00
|
|
|
|
2016-05-05 13:59:07 +01:00
|
|
|
#include <arch.h>
|
|
|
|
#include <arch_helpers.h>
|
2018-12-14 00:18:21 +00:00
|
|
|
#include <drivers/arm/tzc_common.h>
|
|
|
|
#include <lib/mmio.h>
|
2016-01-28 17:22:16 +00:00
|
|
|
|
|
|
|
#define DEFINE_TZC_COMMON_WRITE_ACTION(fn_name, macro_name) \
|
|
|
|
static inline void _tzc##fn_name##_write_action( \
|
|
|
|
uintptr_t base, \
|
2018-10-15 14:58:11 +01:00
|
|
|
unsigned int action) \
|
2016-01-28 17:22:16 +00:00
|
|
|
{ \
|
|
|
|
mmio_write_32(base + TZC_##macro_name##_ACTION_OFF, \
|
|
|
|
action); \
|
|
|
|
}
|
|
|
|
|
|
|
|
#define DEFINE_TZC_COMMON_WRITE_REGION_BASE(fn_name, macro_name) \
|
|
|
|
static inline void _tzc##fn_name##_write_region_base( \
|
2016-04-08 14:40:44 +01:00
|
|
|
uintptr_t base, \
|
2018-10-15 14:58:11 +01:00
|
|
|
unsigned int region_no, \
|
2016-04-08 14:40:44 +01:00
|
|
|
unsigned long long region_base) \
|
2016-01-28 17:22:16 +00:00
|
|
|
{ \
|
|
|
|
mmio_write_32(base + \
|
|
|
|
TZC_REGION_OFFSET( \
|
|
|
|
TZC_##macro_name##_REGION_SIZE, \
|
Increase type widths to satisfy width requirements
Usually, C has no problem up-converting types to larger bit sizes. MISRA
rule 10.7 requires that you not do this, or be very explicit about this.
This resolves the following required rule:
bl1/aarch64/bl1_context_mgmt.c:81:[MISRA C-2012 Rule 10.7 (required)]<None>
The width of the composite expression "0U | ((mode & 3U) << 2U) | 1U |
0x3c0U" (32 bits) is less that the right hand operand
"18446744073709547519ULL" (64 bits).
This also resolves MISRA defects such as:
bl2/aarch64/bl2arch_setup.c:18:[MISRA C-2012 Rule 12.2 (required)]
In the expression "3U << 20", shifting more than 7 bits, the number
of bits in the essential type of the left expression, "3U", is
not allowed.
Further, MISRA requires that all shifts don't overflow. The definition of
PAGE_SIZE was (1U << 12), and 1U is 8 bits. This caused about 50 issues.
This fixes the violation by changing the definition to 1UL << 12. Since
this uses 32bits, it should not create any issues for aarch32.
This patch also contains a fix for a build failure in the sun50i_a64
platform. Specifically, these misra fixes removed a single and
instruction,
92407e73 and x19, x19, #0xffffffff
from the cm_setup_context function caused a relocation in
psci_cpus_on_start to require a linker-generated stub. This increased the
size of the .text section and caused an alignment later on to go over a
page boundary and round up to the end of RAM before placing the .data
section. This sectionn is of non-zero size and therefore causes a link
error.
The fix included in this reorders the functions during link time
without changing their ording with respect to alignment.
Change-Id: I76b4b662c3d262296728a8b9aab7a33b02087f16
Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>
2020-08-04 22:18:52 +01:00
|
|
|
(u_register_t)region_no) + \
|
2016-04-08 14:40:44 +01:00
|
|
|
TZC_##macro_name##_REGION_BASE_LOW_0_OFFSET, \
|
|
|
|
(uint32_t)region_base); \
|
2016-01-28 17:22:16 +00:00
|
|
|
mmio_write_32(base + \
|
|
|
|
TZC_REGION_OFFSET( \
|
|
|
|
TZC_##macro_name##_REGION_SIZE, \
|
Increase type widths to satisfy width requirements
Usually, C has no problem up-converting types to larger bit sizes. MISRA
rule 10.7 requires that you not do this, or be very explicit about this.
This resolves the following required rule:
bl1/aarch64/bl1_context_mgmt.c:81:[MISRA C-2012 Rule 10.7 (required)]<None>
The width of the composite expression "0U | ((mode & 3U) << 2U) | 1U |
0x3c0U" (32 bits) is less that the right hand operand
"18446744073709547519ULL" (64 bits).
This also resolves MISRA defects such as:
bl2/aarch64/bl2arch_setup.c:18:[MISRA C-2012 Rule 12.2 (required)]
In the expression "3U << 20", shifting more than 7 bits, the number
of bits in the essential type of the left expression, "3U", is
not allowed.
Further, MISRA requires that all shifts don't overflow. The definition of
PAGE_SIZE was (1U << 12), and 1U is 8 bits. This caused about 50 issues.
This fixes the violation by changing the definition to 1UL << 12. Since
this uses 32bits, it should not create any issues for aarch32.
This patch also contains a fix for a build failure in the sun50i_a64
platform. Specifically, these misra fixes removed a single and
instruction,
92407e73 and x19, x19, #0xffffffff
from the cm_setup_context function caused a relocation in
psci_cpus_on_start to require a linker-generated stub. This increased the
size of the .text section and caused an alignment later on to go over a
page boundary and round up to the end of RAM before placing the .data
section. This sectionn is of non-zero size and therefore causes a link
error.
The fix included in this reorders the functions during link time
without changing their ording with respect to alignment.
Change-Id: I76b4b662c3d262296728a8b9aab7a33b02087f16
Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>
2020-08-04 22:18:52 +01:00
|
|
|
(u_register_t)region_no) + \
|
2016-01-28 17:22:16 +00:00
|
|
|
TZC_##macro_name##_REGION_BASE_HIGH_0_OFFSET, \
|
2016-04-08 14:40:44 +01:00
|
|
|
(uint32_t)(region_base >> 32)); \
|
2016-01-28 17:22:16 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
#define DEFINE_TZC_COMMON_WRITE_REGION_TOP(fn_name, macro_name) \
|
|
|
|
static inline void _tzc##fn_name##_write_region_top( \
|
2016-04-08 14:40:44 +01:00
|
|
|
uintptr_t base, \
|
2018-10-15 14:58:11 +01:00
|
|
|
unsigned int region_no, \
|
2016-04-08 14:40:44 +01:00
|
|
|
unsigned long long region_top) \
|
2016-01-28 17:22:16 +00:00
|
|
|
{ \
|
|
|
|
mmio_write_32(base + \
|
Increase type widths to satisfy width requirements
Usually, C has no problem up-converting types to larger bit sizes. MISRA
rule 10.7 requires that you not do this, or be very explicit about this.
This resolves the following required rule:
bl1/aarch64/bl1_context_mgmt.c:81:[MISRA C-2012 Rule 10.7 (required)]<None>
The width of the composite expression "0U | ((mode & 3U) << 2U) | 1U |
0x3c0U" (32 bits) is less that the right hand operand
"18446744073709547519ULL" (64 bits).
This also resolves MISRA defects such as:
bl2/aarch64/bl2arch_setup.c:18:[MISRA C-2012 Rule 12.2 (required)]
In the expression "3U << 20", shifting more than 7 bits, the number
of bits in the essential type of the left expression, "3U", is
not allowed.
Further, MISRA requires that all shifts don't overflow. The definition of
PAGE_SIZE was (1U << 12), and 1U is 8 bits. This caused about 50 issues.
This fixes the violation by changing the definition to 1UL << 12. Since
this uses 32bits, it should not create any issues for aarch32.
This patch also contains a fix for a build failure in the sun50i_a64
platform. Specifically, these misra fixes removed a single and
instruction,
92407e73 and x19, x19, #0xffffffff
from the cm_setup_context function caused a relocation in
psci_cpus_on_start to require a linker-generated stub. This increased the
size of the .text section and caused an alignment later on to go over a
page boundary and round up to the end of RAM before placing the .data
section. This sectionn is of non-zero size and therefore causes a link
error.
The fix included in this reorders the functions during link time
without changing their ording with respect to alignment.
Change-Id: I76b4b662c3d262296728a8b9aab7a33b02087f16
Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>
2020-08-04 22:18:52 +01:00
|
|
|
TZC_REGION_OFFSET( \
|
|
|
|
TZC_##macro_name##_REGION_SIZE, \
|
|
|
|
(u_register_t)region_no) + \
|
2016-01-28 17:22:16 +00:00
|
|
|
TZC_##macro_name##_REGION_TOP_LOW_0_OFFSET, \
|
2018-10-15 14:58:11 +01:00
|
|
|
(uint32_t)region_top); \
|
2016-01-28 17:22:16 +00:00
|
|
|
mmio_write_32(base + \
|
|
|
|
TZC_REGION_OFFSET( \
|
|
|
|
TZC_##macro_name##_REGION_SIZE, \
|
Increase type widths to satisfy width requirements
Usually, C has no problem up-converting types to larger bit sizes. MISRA
rule 10.7 requires that you not do this, or be very explicit about this.
This resolves the following required rule:
bl1/aarch64/bl1_context_mgmt.c:81:[MISRA C-2012 Rule 10.7 (required)]<None>
The width of the composite expression "0U | ((mode & 3U) << 2U) | 1U |
0x3c0U" (32 bits) is less that the right hand operand
"18446744073709547519ULL" (64 bits).
This also resolves MISRA defects such as:
bl2/aarch64/bl2arch_setup.c:18:[MISRA C-2012 Rule 12.2 (required)]
In the expression "3U << 20", shifting more than 7 bits, the number
of bits in the essential type of the left expression, "3U", is
not allowed.
Further, MISRA requires that all shifts don't overflow. The definition of
PAGE_SIZE was (1U << 12), and 1U is 8 bits. This caused about 50 issues.
This fixes the violation by changing the definition to 1UL << 12. Since
this uses 32bits, it should not create any issues for aarch32.
This patch also contains a fix for a build failure in the sun50i_a64
platform. Specifically, these misra fixes removed a single and
instruction,
92407e73 and x19, x19, #0xffffffff
from the cm_setup_context function caused a relocation in
psci_cpus_on_start to require a linker-generated stub. This increased the
size of the .text section and caused an alignment later on to go over a
page boundary and round up to the end of RAM before placing the .data
section. This sectionn is of non-zero size and therefore causes a link
error.
The fix included in this reorders the functions during link time
without changing their ording with respect to alignment.
Change-Id: I76b4b662c3d262296728a8b9aab7a33b02087f16
Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>
2020-08-04 22:18:52 +01:00
|
|
|
(u_register_t)region_no) + \
|
2016-01-28 17:22:16 +00:00
|
|
|
TZC_##macro_name##_REGION_TOP_HIGH_0_OFFSET, \
|
2018-10-15 14:58:11 +01:00
|
|
|
(uint32_t)(region_top >> 32)); \
|
2016-01-28 17:22:16 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
#define DEFINE_TZC_COMMON_WRITE_REGION_ATTRIBUTES(fn_name, macro_name) \
|
|
|
|
static inline void _tzc##fn_name##_write_region_attributes( \
|
|
|
|
uintptr_t base, \
|
2018-10-15 14:58:11 +01:00
|
|
|
unsigned int region_no, \
|
2016-01-28 17:22:16 +00:00
|
|
|
unsigned int attr) \
|
|
|
|
{ \
|
|
|
|
mmio_write_32(base + \
|
|
|
|
TZC_REGION_OFFSET( \
|
|
|
|
TZC_##macro_name##_REGION_SIZE, \
|
Increase type widths to satisfy width requirements
Usually, C has no problem up-converting types to larger bit sizes. MISRA
rule 10.7 requires that you not do this, or be very explicit about this.
This resolves the following required rule:
bl1/aarch64/bl1_context_mgmt.c:81:[MISRA C-2012 Rule 10.7 (required)]<None>
The width of the composite expression "0U | ((mode & 3U) << 2U) | 1U |
0x3c0U" (32 bits) is less that the right hand operand
"18446744073709547519ULL" (64 bits).
This also resolves MISRA defects such as:
bl2/aarch64/bl2arch_setup.c:18:[MISRA C-2012 Rule 12.2 (required)]
In the expression "3U << 20", shifting more than 7 bits, the number
of bits in the essential type of the left expression, "3U", is
not allowed.
Further, MISRA requires that all shifts don't overflow. The definition of
PAGE_SIZE was (1U << 12), and 1U is 8 bits. This caused about 50 issues.
This fixes the violation by changing the definition to 1UL << 12. Since
this uses 32bits, it should not create any issues for aarch32.
This patch also contains a fix for a build failure in the sun50i_a64
platform. Specifically, these misra fixes removed a single and
instruction,
92407e73 and x19, x19, #0xffffffff
from the cm_setup_context function caused a relocation in
psci_cpus_on_start to require a linker-generated stub. This increased the
size of the .text section and caused an alignment later on to go over a
page boundary and round up to the end of RAM before placing the .data
section. This sectionn is of non-zero size and therefore causes a link
error.
The fix included in this reorders the functions during link time
without changing their ording with respect to alignment.
Change-Id: I76b4b662c3d262296728a8b9aab7a33b02087f16
Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>
2020-08-04 22:18:52 +01:00
|
|
|
(u_register_t)region_no) + \
|
2016-01-28 17:22:16 +00:00
|
|
|
TZC_##macro_name##_REGION_ATTR_0_OFFSET, \
|
|
|
|
attr); \
|
|
|
|
}
|
|
|
|
|
|
|
|
#define DEFINE_TZC_COMMON_WRITE_REGION_ID_ACCESS(fn_name, macro_name) \
|
|
|
|
static inline void _tzc##fn_name##_write_region_id_access( \
|
|
|
|
uintptr_t base, \
|
2018-10-15 14:58:11 +01:00
|
|
|
unsigned int region_no, \
|
2016-01-28 17:22:16 +00:00
|
|
|
unsigned int val) \
|
|
|
|
{ \
|
|
|
|
mmio_write_32(base + \
|
|
|
|
TZC_REGION_OFFSET( \
|
|
|
|
TZC_##macro_name##_REGION_SIZE, \
|
Increase type widths to satisfy width requirements
Usually, C has no problem up-converting types to larger bit sizes. MISRA
rule 10.7 requires that you not do this, or be very explicit about this.
This resolves the following required rule:
bl1/aarch64/bl1_context_mgmt.c:81:[MISRA C-2012 Rule 10.7 (required)]<None>
The width of the composite expression "0U | ((mode & 3U) << 2U) | 1U |
0x3c0U" (32 bits) is less that the right hand operand
"18446744073709547519ULL" (64 bits).
This also resolves MISRA defects such as:
bl2/aarch64/bl2arch_setup.c:18:[MISRA C-2012 Rule 12.2 (required)]
In the expression "3U << 20", shifting more than 7 bits, the number
of bits in the essential type of the left expression, "3U", is
not allowed.
Further, MISRA requires that all shifts don't overflow. The definition of
PAGE_SIZE was (1U << 12), and 1U is 8 bits. This caused about 50 issues.
This fixes the violation by changing the definition to 1UL << 12. Since
this uses 32bits, it should not create any issues for aarch32.
This patch also contains a fix for a build failure in the sun50i_a64
platform. Specifically, these misra fixes removed a single and
instruction,
92407e73 and x19, x19, #0xffffffff
from the cm_setup_context function caused a relocation in
psci_cpus_on_start to require a linker-generated stub. This increased the
size of the .text section and caused an alignment later on to go over a
page boundary and round up to the end of RAM before placing the .data
section. This sectionn is of non-zero size and therefore causes a link
error.
The fix included in this reorders the functions during link time
without changing their ording with respect to alignment.
Change-Id: I76b4b662c3d262296728a8b9aab7a33b02087f16
Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>
2020-08-04 22:18:52 +01:00
|
|
|
(u_register_t)region_no) + \
|
2016-01-28 17:22:16 +00:00
|
|
|
TZC_##macro_name##_REGION_ID_ACCESS_0_OFFSET, \
|
|
|
|
val); \
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* It is used to program region 0 ATTRIBUTES and ACCESS register.
|
|
|
|
*/
|
|
|
|
#define DEFINE_TZC_COMMON_CONFIGURE_REGION0(fn_name) \
|
2018-02-12 12:36:17 +00:00
|
|
|
static void _tzc##fn_name##_configure_region0(uintptr_t base, \
|
2018-10-15 14:58:11 +01:00
|
|
|
unsigned int sec_attr, \
|
2016-01-28 17:22:16 +00:00
|
|
|
unsigned int ns_device_access) \
|
|
|
|
{ \
|
2018-10-15 14:58:11 +01:00
|
|
|
assert(base != 0U); \
|
2016-01-28 17:22:16 +00:00
|
|
|
VERBOSE("TrustZone : Configuring region 0 " \
|
2018-10-15 14:58:11 +01:00
|
|
|
"(TZC Interface Base=0x%lx sec_attr=0x%x," \
|
|
|
|
" ns_devs=0x%x)\n", base, \
|
2016-01-28 17:22:16 +00:00
|
|
|
sec_attr, ns_device_access); \
|
|
|
|
\
|
|
|
|
/* Set secure attributes on region 0 */ \
|
|
|
|
_tzc##fn_name##_write_region_attributes(base, 0, \
|
|
|
|
sec_attr << TZC_REGION_ATTR_SEC_SHIFT); \
|
|
|
|
\
|
|
|
|
/***************************************************/ \
|
|
|
|
/* Specify which non-secure devices have permission*/ \
|
|
|
|
/* to access region 0. */ \
|
|
|
|
/***************************************************/ \
|
|
|
|
_tzc##fn_name##_write_region_id_access(base, \
|
|
|
|
0, \
|
|
|
|
ns_device_access); \
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* It is used to program a region from 1 to 8 in the TrustZone controller.
|
|
|
|
* NOTE:
|
|
|
|
* Region 0 is special; it is preferable to use
|
|
|
|
* ##fn_name##_configure_region0 for this region (see comment for
|
|
|
|
* that function).
|
|
|
|
*/
|
|
|
|
#define DEFINE_TZC_COMMON_CONFIGURE_REGION(fn_name) \
|
2018-02-12 12:36:17 +00:00
|
|
|
static void _tzc##fn_name##_configure_region(uintptr_t base, \
|
2016-01-28 17:22:16 +00:00
|
|
|
unsigned int filters, \
|
2018-10-15 14:58:11 +01:00
|
|
|
unsigned int region_no, \
|
2016-04-08 14:40:44 +01:00
|
|
|
unsigned long long region_base, \
|
|
|
|
unsigned long long region_top, \
|
2018-10-15 14:58:11 +01:00
|
|
|
unsigned int sec_attr, \
|
|
|
|
unsigned int nsaid_permissions) \
|
2016-01-28 17:22:16 +00:00
|
|
|
{ \
|
2018-10-15 14:58:11 +01:00
|
|
|
assert(base != 0U); \
|
2016-01-28 17:22:16 +00:00
|
|
|
VERBOSE("TrustZone : Configuring region " \
|
2018-10-15 14:58:11 +01:00
|
|
|
"(TZC Interface Base: 0x%lx, region_no = %u)" \
|
|
|
|
"...\n", base, region_no); \
|
2016-04-08 14:40:44 +01:00
|
|
|
VERBOSE("TrustZone : ... base = %llx, top = %llx," \
|
2018-10-15 14:58:11 +01:00
|
|
|
"\n", region_base, region_top); \
|
2016-01-28 17:22:16 +00:00
|
|
|
VERBOSE("TrustZone : ... sec_attr = 0x%x," \
|
|
|
|
" ns_devs = 0x%x)\n", \
|
|
|
|
sec_attr, nsaid_permissions); \
|
|
|
|
\
|
|
|
|
/***************************************************/ \
|
|
|
|
/* Inputs look ok, start programming registers. */ \
|
|
|
|
/* All the address registers are 32 bits wide and */ \
|
|
|
|
/* have a LOW and HIGH */ \
|
|
|
|
/* component used to construct an address up to a */ \
|
|
|
|
/* 64bit. */ \
|
|
|
|
/***************************************************/ \
|
|
|
|
_tzc##fn_name##_write_region_base(base, \
|
|
|
|
region_no, region_base); \
|
|
|
|
_tzc##fn_name##_write_region_top(base, \
|
|
|
|
region_no, region_top); \
|
|
|
|
\
|
|
|
|
/* Enable filter to the region and set secure attributes */\
|
|
|
|
_tzc##fn_name##_write_region_attributes(base, \
|
|
|
|
region_no, \
|
|
|
|
(sec_attr << TZC_REGION_ATTR_SEC_SHIFT) |\
|
|
|
|
(filters << TZC_REGION_ATTR_F_EN_SHIFT));\
|
|
|
|
\
|
|
|
|
/***************************************************/ \
|
|
|
|
/* Specify which non-secure devices have permission*/ \
|
|
|
|
/* to access this region. */ \
|
|
|
|
/***************************************************/ \
|
|
|
|
_tzc##fn_name##_write_region_id_access(base, \
|
|
|
|
region_no, \
|
|
|
|
nsaid_permissions); \
|
|
|
|
}
|
|
|
|
|
2017-02-28 10:58:25 +00:00
|
|
|
static inline unsigned int _tzc_read_peripheral_id(uintptr_t base)
|
2016-01-28 17:22:16 +00:00
|
|
|
{
|
|
|
|
unsigned int id;
|
|
|
|
|
|
|
|
id = mmio_read_32(base + PID0_OFF);
|
|
|
|
/* Masks DESC part in PID1 */
|
2018-10-15 14:58:11 +01:00
|
|
|
id |= ((mmio_read_32(base + PID1_OFF) & 0xFU) << 8U);
|
2016-01-28 17:22:16 +00:00
|
|
|
|
|
|
|
return id;
|
|
|
|
}
|
2016-05-05 13:59:07 +01:00
|
|
|
|
2018-10-15 14:58:11 +01:00
|
|
|
#endif /* TZC_COMMON_PRIVATE_H */
|