2019-10-23 09:26:53 +01:00
|
|
|
/*
|
|
|
|
* Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
|
|
|
|
*
|
|
|
|
* SPDX-License-Identifier: BSD-3-Clause
|
|
|
|
*/
|
|
|
|
|
|
|
|
#ifndef PLAT_SOCFPGA_DEF_H
|
|
|
|
#define PLAT_SOCFPGA_DEF_H
|
|
|
|
|
|
|
|
#include <platform_def.h>
|
|
|
|
|
|
|
|
/* Platform Setting */
|
2019-12-30 08:00:30 +00:00
|
|
|
#define PLATFORM_MODEL PLAT_SOCFPGA_STRATIX10
|
|
|
|
#define BOOT_SOURCE BOOT_SOURCE_SDMMC
|
2019-10-23 09:26:53 +01:00
|
|
|
|
|
|
|
/* Register Mapping */
|
|
|
|
#define SOCFPGA_MMC_REG_BASE 0xff808000
|
2019-12-23 09:58:04 +00:00
|
|
|
|
2019-12-23 05:25:33 +00:00
|
|
|
#define SOCFPGA_RSTMGR_REG_BASE 0xffd11000
|
2019-12-23 09:58:04 +00:00
|
|
|
#define SOCFPGA_SYSMGR_REG_BASE 0xffd12000
|
|
|
|
|
|
|
|
#define SOCFPGA_L4_PER_SCR_REG_BASE 0xffd21000
|
|
|
|
#define SOCFPGA_L4_SYS_SCR_REG_BASE 0xffd21100
|
|
|
|
#define SOCFPGA_SOC2FPGA_SCR_REG_BASE 0xffd21200
|
|
|
|
#define SOCFPGA_LWSOC2FPGA_SCR_REG_BASE 0xffd21300
|
|
|
|
|
2019-10-23 09:26:53 +01:00
|
|
|
|
|
|
|
#endif /* PLATSOCFPGA_DEF_H */
|
|
|
|
|