2018-05-04 15:09:47 +01:00
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/*
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2020-06-03 21:23:31 +01:00
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* Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
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2018-05-04 15:09:47 +01:00
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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2019-07-03 12:02:56 +01:00
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#ifndef CORTEX_A77_H
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#define CORTEX_A77_H
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2018-05-04 15:09:47 +01:00
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2019-02-11 13:34:15 +00:00
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#include <lib/utils_def.h>
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2019-07-03 12:02:56 +01:00
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/* Cortex-A77 MIDR */
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#define CORTEX_A77_MIDR U(0x410FD0D0)
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2018-05-04 15:09:47 +01:00
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/*******************************************************************************
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* CPU Extended Control register specific definitions.
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******************************************************************************/
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2019-07-03 12:02:56 +01:00
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#define CORTEX_A77_CPUECTLR_EL1 S3_0_C15_C1_4
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2020-09-10 19:39:26 +01:00
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#define CORTEX_A77_CPUECTLR_EL1_BIT_8 (ULL(1) << 8)
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2018-05-04 15:09:47 +01:00
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/*******************************************************************************
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* CPU Power Control register specific definitions.
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******************************************************************************/
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2019-07-03 12:02:56 +01:00
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#define CORTEX_A77_CPUPWRCTLR_EL1 S3_0_C15_C2_7
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#define CORTEX_A77_CPUPWRCTLR_EL1_CORE_PWRDN_BIT (U(1) << 0)
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2018-05-04 15:09:47 +01:00
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2020-07-14 20:18:34 +01:00
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#define CORTEX_A77_CPUPSELR_EL3 S3_6_C15_C8_0
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#define CORTEX_A77_CPUPCR_EL3 S3_6_C15_C8_1
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#define CORTEX_A77_CPUPOR_EL3 S3_6_C15_C8_2
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#define CORTEX_A77_CPUPMR_EL3 S3_6_C15_C8_3
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#define CORTEX_A77_CPUPOR2_EL3 S3_6_C15_C8_4
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#define CORTEX_A77_CPUPMR2_EL3 S3_6_C15_C8_5
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2019-07-03 12:02:56 +01:00
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#endif /* CORTEX_A77_H */
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