113 lines
3.2 KiB
ArmAsm
113 lines
3.2 KiB
ArmAsm
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/*
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* Copyright (C) 2018 Marvell International Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* https://spdx.org/licenses
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*/
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#include <asm_macros.S>
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#include <platform_def.h>
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#include <marvell_pm.h>
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.globl plat_secondary_cold_boot_setup
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.globl plat_get_my_entrypoint
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.globl plat_is_my_cpu_primary
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.globl plat_reset_handler
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/* -----------------------------------------------------
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* void plat_secondary_cold_boot_setup (void);
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*
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* This function performs any platform specific actions
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* needed for a secondary cpu after a cold reset. Right
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* now this is a stub function.
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* -----------------------------------------------------
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*/
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func plat_secondary_cold_boot_setup
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mov x0, #0
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ret
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endfunc plat_secondary_cold_boot_setup
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/* ---------------------------------------------------------------------
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* unsigned long plat_get_my_entrypoint (void);
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*
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* Main job of this routine is to distinguish
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* between a cold and warm boot
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* For a cold boot, return 0.
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* For a warm boot, read the mailbox and return the address it contains.
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*
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* ---------------------------------------------------------------------
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*/
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func plat_get_my_entrypoint
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/* Read first word and compare it with magic num */
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mov_imm x0, PLAT_MARVELL_MAILBOX_BASE
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ldr x1, [x0]
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mov_imm x2, MVEBU_MAILBOX_MAGIC_NUM
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cmp x1, x2
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beq warm_boot /* If compare failed, return 0, i.e. cold boot */
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mov x0, #0
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ret
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warm_boot:
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mov_imm x1, MBOX_IDX_SEC_ADDR /* Get the jump address */
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subs x1, x1, #1
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mov x2, #(MBOX_IDX_SEC_ADDR * 8)
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lsl x3, x2, x1
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add x0, x0, x3
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ldr x0, [x0]
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ret
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endfunc plat_get_my_entrypoint
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/* -----------------------------------------------------
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* unsigned int plat_is_my_cpu_primary (void);
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*
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* Find out whether the current cpu is the primary
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* cpu.
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* -----------------------------------------------------
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*/
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func plat_is_my_cpu_primary
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mrs x0, mpidr_el1
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and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)
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cmp x0, #MVEBU_PRIMARY_CPU
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cset w0, eq
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ret
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endfunc plat_is_my_cpu_primary
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/* -----------------------------------------------------
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* void plat_reset_handler (void);
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*
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* Platform specific configuration right after cpu is
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* is our of reset.
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*
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* The plat_reset_handler can clobber x0 - x18, x30.
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* -----------------------------------------------------
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*/
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func plat_reset_handler
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/*
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* Note: the configurations below should be done before MMU,
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* I Cache and L2are enabled.
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* The reset handler is executed right after reset
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* and before Caches are enabled.
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*/
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/* Enable L1/L2 ECC and Parity */
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mrs x5, s3_1_c11_c0_2 /* L2 Ctrl */
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orr x5, x5, #(1 << 21) /* Enable L1/L2 cache ECC & Parity */
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msr s3_1_c11_c0_2, x5 /* L2 Ctrl */
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#if LLC_ENABLE
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/*
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* Enable L2 UniqueClean evictions
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* Note: this configuration assumes that LLC is configured
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* in exclusive mode.
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* Later on in the code this assumption will be validated
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*/
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mrs x5, s3_1_c15_c0_0 /* L2 Ctrl */
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orr x5, x5, #(1 << 14) /* Enable UniqueClean evictions with data */
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msr s3_1_c15_c0_0, x5 /* L2 Ctrl */
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#endif
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/* Instruction Barrier to allow msr command completion */
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isb
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ret
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endfunc plat_reset_handler
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