2016-07-11 14:15:27 +01:00
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/*
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2018-01-10 15:59:31 +00:00
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* Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
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2016-07-11 14:15:27 +01:00
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*
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2017-05-03 09:38:09 +01:00
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* SPDX-License-Identifier: BSD-3-Clause
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2016-07-11 14:15:27 +01:00
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*/
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2019-01-25 14:30:04 +00:00
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#include <plat/arm/common/plat_arm.h>
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2016-07-11 14:15:27 +01:00
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#include "../fvp_private.h"
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2018-03-01 10:53:33 +00:00
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void plat_arm_sp_min_early_platform_setup(u_register_t arg0, u_register_t arg1,
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2018-01-10 15:59:31 +00:00
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u_register_t arg2, u_register_t arg3)
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2016-07-11 14:15:27 +01:00
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{
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2018-01-10 15:59:31 +00:00
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arm_sp_min_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3);
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2016-07-11 14:15:27 +01:00
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/* Initialize the platform config for future decision making */
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fvp_config_setup();
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/*
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* Initialize the correct interconnect for this cluster during cold
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* boot. No need for locks as no other CPU is active.
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*/
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fvp_interconnect_init();
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/*
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* Enable coherency in interconnect for the primary CPU's cluster.
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* Earlier bootloader stages might already do this (e.g. Trusted
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* Firmware's BL1 does it) but we can't assume so. There is no harm in
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* executing this code twice anyway.
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* FVP PSCI code will enable coherency for other clusters.
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*/
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fvp_interconnect_enable();
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}
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