2016-01-15 09:17:32 +00:00
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/*
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* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __PMU_COM_H__
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#define __PMU_COM_H__
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2016-04-10 07:11:07 +01:00
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/*
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* Use this macro to instantiate lock before it is used in below
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* rockchip_pd_lock_xxx() macros
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*/
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2016-07-16 04:16:51 +01:00
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DECLARE_BAKERY_LOCK(rockchip_pd_lock);
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2016-01-15 09:17:32 +00:00
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2016-04-10 07:11:07 +01:00
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/*
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* These are wrapper macros to the powe domain Bakery Lock API.
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*/
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#define rockchip_pd_lock_init() bakery_lock_init(&rockchip_pd_lock)
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2016-01-15 09:17:32 +00:00
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#define rockchip_pd_lock_get() bakery_lock_get(&rockchip_pd_lock)
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#define rockchip_pd_lock_rls() bakery_lock_release(&rockchip_pd_lock)
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/*****************************************************************************
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* power domain on or off
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*****************************************************************************/
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enum pmu_pd_state {
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pmu_pd_on = 0,
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pmu_pd_off = 1
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};
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#pragma weak plat_ic_get_pending_interrupt_id
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#pragma weak pmu_power_domain_ctr
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#pragma weak check_cpu_wfie
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static inline uint32_t pmu_power_domain_st(uint32_t pd)
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{
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uint32_t pwrdn_st = mmio_read_32(PMU_BASE + PMU_PWRDN_ST) & BIT(pd);
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if (pwrdn_st)
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return pmu_pd_off;
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else
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return pmu_pd_on;
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}
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static int pmu_power_domain_ctr(uint32_t pd, uint32_t pd_state)
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{
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uint32_t val;
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uint32_t loop = 0;
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int ret = 0;
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rockchip_pd_lock_get();
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val = mmio_read_32(PMU_BASE + PMU_PWRDN_CON);
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if (pd_state == pmu_pd_off)
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val |= BIT(pd);
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else
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val &= ~BIT(pd);
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mmio_write_32(PMU_BASE + PMU_PWRDN_CON, val);
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dsb();
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while ((pmu_power_domain_st(pd) != pd_state) && (loop < PD_CTR_LOOP)) {
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udelay(1);
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loop++;
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}
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if (pmu_power_domain_st(pd) != pd_state) {
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WARN("%s: %d, %d, error!\n", __func__, pd, pd_state);
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ret = -EINVAL;
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}
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rockchip_pd_lock_rls();
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return ret;
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}
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static int check_cpu_wfie(uint32_t cpu_id, uint32_t wfie_msk)
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{
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uint32_t cluster_id, loop = 0;
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if (cpu_id >= PLATFORM_CLUSTER0_CORE_COUNT) {
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cluster_id = 1;
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cpu_id -= PLATFORM_CLUSTER0_CORE_COUNT;
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} else {
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cluster_id = 0;
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}
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if (cluster_id)
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wfie_msk <<= (clstb_cpu_wfe + cpu_id);
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else
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wfie_msk <<= (clstl_cpu_wfe + cpu_id);
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while (!(mmio_read_32(PMU_BASE + PMU_CORE_PWR_ST) & wfie_msk) &&
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(loop < CHK_CPU_LOOP)) {
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udelay(1);
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loop++;
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}
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if ((mmio_read_32(PMU_BASE + PMU_CORE_PWR_ST) & wfie_msk) == 0) {
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WARN("%s: %d, %d, %d, error!\n", __func__,
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cluster_id, cpu_id, wfie_msk);
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return -EINVAL;
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}
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return 0;
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}
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#endif /* __PMU_COM_H__ */
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