2016-08-25 01:37:42 +01:00
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/*
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* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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2016-10-26 18:12:34 +01:00
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#ifndef __SOC_ROCKCHIP_RK3399_DRAM_H__
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#define __SOC_ROCKCHIP_RK3399_DRAM_H__
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#include <plat_private.h>
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#include <stdint.h>
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#define CTL_BASE(ch) (0xffa80000 + (ch) * 0x8000)
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#define CTL_REG(ch, n) (CTL_BASE(ch) + (n) * 0x4)
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#define PI_OFFSET 0x800
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#define PI_BASE(ch) (CTL_BASE(ch) + PI_OFFSET)
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#define PI_REG(ch, n) (PI_BASE(ch) + (n) * 0x4)
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#define PHY_OFFSET 0x2000
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#define PHY_BASE(ch) (CTL_BASE(ch) + PHY_OFFSET)
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#define PHY_REG(ch, n) (PHY_BASE(ch) + (n) * 0x4)
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#define MSCH_BASE(ch) (0xffa84000 + (ch) * 0x8000)
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#define MSCH_ID_COREID 0x0
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#define MSCH_ID_REVISIONID 0x4
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#define MSCH_DEVICECONF 0x8
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#define MSCH_DEVICESIZE 0xc
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#define MSCH_DDRTIMINGA0 0x10
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#define MSCH_DDRTIMINGB0 0x14
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#define MSCH_DDRTIMINGC0 0x18
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#define MSCH_DEVTODEV0 0x1c
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#define MSCH_DDRMODE 0x110
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#define MSCH_AGINGX0 0x1000
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#define CIC_CTRL0 0x0
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#define CIC_CTRL1 0x4
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#define CIC_IDLE_TH 0x8
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#define CIC_CG_WAIT_TH 0xc
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#define CIC_STATUS0 0x10
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#define CIC_STATUS1 0x14
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#define CIC_CTRL2 0x18
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#define CIC_CTRL3 0x1c
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#define CIC_CTRL4 0x20
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2016-08-25 01:37:42 +01:00
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/* DENALI_CTL_00 */
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2016-10-26 18:12:34 +01:00
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#define START 1
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2016-08-25 01:37:42 +01:00
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/* DENALI_CTL_68 */
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#define PWRUP_SREFRESH_EXIT (1 << 16)
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/* DENALI_CTL_274 */
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2016-10-26 18:12:34 +01:00
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#define MEM_RST_VALID 1
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#define PHY_DRV_ODT_Hi_Z 0x0
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#define PHY_DRV_ODT_240 0x1
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#define PHY_DRV_ODT_120 0x8
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#define PHY_DRV_ODT_80 0x9
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#define PHY_DRV_ODT_60 0xc
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#define PHY_DRV_ODT_48 0xd
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#define PHY_DRV_ODT_40 0xe
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#define PHY_DRV_ODT_34_3 0xf
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/*
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* sys_reg bitfield struct
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* [31] row_3_4_ch1
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* [30] row_3_4_ch0
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* [29:28] chinfo
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* [27] rank_ch1
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* [26:25] col_ch1
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* [24] bk_ch1
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* [23:22] cs0_row_ch1
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* [21:20] cs1_row_ch1
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* [19:18] bw_ch1
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* [17:16] dbw_ch1;
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* [15:13] ddrtype
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* [12] channelnum
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* [11] rank_ch0
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* [10:9] col_ch0
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* [8] bk_ch0
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* [7:6] cs0_row_ch0
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* [5:4] cs1_row_ch0
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* [3:2] bw_ch0
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* [1:0] dbw_ch0
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*/
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#define SYS_REG_ENC_ROW_3_4(n, ch) ((n) << (30 + (ch)))
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#define SYS_REG_DEC_ROW_3_4(n, ch) (((n) >> (30 + (ch))) & 0x1)
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#define SYS_REG_ENC_CHINFO(ch) (1 << (28 + (ch)))
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#define SYS_REG_DEC_CHINFO(n, ch) (((n) >> (28 + (ch))) & 0x1)
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#define SYS_REG_ENC_DDRTYPE(n) ((n) << 13)
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#define SYS_REG_DEC_DDRTYPE(n) (((n) >> 13) & 0x7)
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#define SYS_REG_ENC_NUM_CH(n) (((n) - 1) << 12)
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#define SYS_REG_DEC_NUM_CH(n) (1 + (((n) >> 12) & 0x1))
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#define SYS_REG_ENC_RANK(n, ch) (((n) - 1) << (11 + (ch) * 16))
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#define SYS_REG_DEC_RANK(n, ch) (1 + (((n) >> (11 + (ch) * 16)) & 0x1))
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#define SYS_REG_ENC_COL(n, ch) (((n) - 9) << (9 + (ch) * 16))
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#define SYS_REG_DEC_COL(n, ch) (9 + (((n) >> (9 + (ch) * 16)) & 0x3))
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#define SYS_REG_ENC_BK(n, ch) (((n) == 3 ? 0 : 1) << (8 + (ch) * 16))
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#define SYS_REG_DEC_BK(n, ch) (3 - (((n) >> (8 + (ch) * 16)) & 0x1))
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#define SYS_REG_ENC_CS0_ROW(n, ch) (((n) - 13) << (6 + (ch) * 16))
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#define SYS_REG_DEC_CS0_ROW(n, ch) (13 + (((n) >> (6 + (ch) * 16)) & 0x3))
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#define SYS_REG_ENC_CS1_ROW(n, ch) (((n) - 13) << (4 + (ch) * 16))
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#define SYS_REG_DEC_CS1_ROW(n, ch) (13 + (((n) >> (4 + (ch) * 16)) & 0x3))
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#define SYS_REG_ENC_BW(n, ch) ((2 >> (n)) << (2 + (ch) * 16))
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#define SYS_REG_DEC_BW(n, ch) (2 >> (((n) >> (2 + (ch) * 16)) & 0x3))
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#define SYS_REG_ENC_DBW(n, ch) ((2 >> (n)) << (0 + (ch) * 16))
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#define SYS_REG_DEC_DBW(n, ch) (2 >> (((n) >> (0 + (ch) * 16)) & 0x3))
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#define DDR_STRIDE(n) mmio_write_32(SGRF_BASE + SGRF_SOC_CON3_7(4), \
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(0x1f<<(10+16))|((n)<<10))
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#define CTL_REG_NUM 332
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#define PHY_REG_NUM 959
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#define PI_REG_NUM 200
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enum {
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DDR3 = 3,
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LPDDR2 = 5,
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LPDDR3 = 6,
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LPDDR4 = 7,
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UNUSED = 0xff
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};
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2016-08-25 01:37:42 +01:00
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struct rk3399_ddr_pctl_regs {
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2016-10-26 18:12:34 +01:00
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uint32_t denali_ctl[CTL_REG_NUM];
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2016-08-25 01:37:42 +01:00
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};
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struct rk3399_ddr_publ_regs {
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2016-10-26 18:12:34 +01:00
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uint32_t denali_phy[PHY_REG_NUM];
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2016-08-25 01:37:42 +01:00
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};
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struct rk3399_ddr_pi_regs {
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2016-10-26 18:12:34 +01:00
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uint32_t denali_pi[PI_REG_NUM];
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2016-08-25 01:37:42 +01:00
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};
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union noc_ddrtiminga0 {
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uint32_t d32;
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struct {
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unsigned acttoact : 6;
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unsigned reserved0 : 2;
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unsigned rdtomiss : 6;
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unsigned reserved1 : 2;
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unsigned wrtomiss : 6;
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unsigned reserved2 : 2;
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unsigned readlatency : 8;
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} b;
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};
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union noc_ddrtimingb0 {
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uint32_t d32;
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struct {
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unsigned rdtowr : 5;
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unsigned reserved0 : 3;
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unsigned wrtord : 5;
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unsigned reserved1 : 3;
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unsigned rrd : 4;
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unsigned reserved2 : 4;
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unsigned faw : 6;
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unsigned reserved3 : 2;
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} b;
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};
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union noc_ddrtimingc0 {
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uint32_t d32;
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struct {
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unsigned burstpenalty : 4;
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unsigned reserved0 : 4;
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unsigned wrtomwr : 6;
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unsigned reserved1 : 18;
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} b;
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};
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union noc_devtodev0 {
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uint32_t d32;
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struct {
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unsigned busrdtord : 3;
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unsigned reserved0 : 1;
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unsigned busrdtowr : 3;
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unsigned reserved1 : 1;
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unsigned buswrtord : 3;
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unsigned reserved2 : 1;
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unsigned buswrtowr : 3;
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unsigned reserved3 : 17;
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} b;
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};
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union noc_ddrmode {
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uint32_t d32;
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struct {
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unsigned autoprecharge : 1;
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unsigned bypassfiltering : 1;
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unsigned fawbank : 1;
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unsigned burstsize : 2;
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unsigned mwrsize : 2;
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unsigned reserved2 : 1;
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unsigned forceorder : 8;
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unsigned forceorderstate : 8;
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unsigned reserved3 : 8;
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} b;
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};
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struct rk3399_msch_timings {
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union noc_ddrtiminga0 ddrtiminga0;
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union noc_ddrtimingb0 ddrtimingb0;
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union noc_ddrtimingc0 ddrtimingc0;
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union noc_devtodev0 devtodev0;
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union noc_ddrmode ddrmode;
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uint32_t agingx0;
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};
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2016-10-26 18:12:34 +01:00
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2016-08-25 01:37:42 +01:00
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struct rk3399_sdram_channel {
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unsigned char rank;
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/* col = 0, means this channel is invalid */
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unsigned char col;
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/* 3:8bank, 2:4bank */
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unsigned char bk;
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/* channel buswidth, 2:32bit, 1:16bit, 0:8bit */
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unsigned char bw;
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/* die buswidth, 2:32bit, 1:16bit, 0:8bit */
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unsigned char dbw;
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/* row_3_4 = 1: 6Gb or 12Gb die
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* row_3_4 = 0: normal die, power of 2
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*/
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unsigned char row_3_4;
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unsigned char cs0_row;
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unsigned char cs1_row;
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uint32_t ddrconfig;
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struct rk3399_msch_timings noc_timings;
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};
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struct rk3399_sdram_params {
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struct rk3399_sdram_channel ch[2];
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uint32_t ddr_freq;
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unsigned char dramtype;
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unsigned char num_channels;
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unsigned char stride;
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unsigned char odt;
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struct rk3399_ddr_pctl_regs pctl_regs;
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struct rk3399_ddr_pi_regs pi_regs;
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struct rk3399_ddr_publ_regs phy_regs;
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};
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2016-10-26 18:12:34 +01:00
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extern __sramdata struct rk3399_sdram_params sdram_config;
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2016-08-25 01:37:42 +01:00
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2016-10-26 18:12:34 +01:00
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void dram_init(void);
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2016-08-25 01:37:42 +01:00
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#endif
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