120 lines
4.3 KiB
C
120 lines
4.3 KiB
C
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/*
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* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __TZC_COMMON_H__
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#define __TZC_COMMON_H__
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/*
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* Offset of core registers from the start of the base of configuration
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* registers for each region.
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*/
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/* ID Registers */
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#define PID0_OFF 0xfe0
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#define PID1_OFF 0xfe4
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#define PID2_OFF 0xfe8
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#define PID3_OFF 0xfec
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#define PID4_OFF 0xfd0
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#define CID0_OFF 0xff0
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#define CID1_OFF 0xff4
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#define CID2_OFF 0xff8
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#define CID3_OFF 0xffc
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/* Bit positions of TZC_ACTION registers */
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#define TZC_ACTION_RV_SHIFT 0
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#define TZC_ACTION_RV_MASK 0x3
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#define TZC_ACTION_RV_LOWOK 0x0
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#define TZC_ACTION_RV_LOWERR 0x1
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#define TZC_ACTION_RV_HIGHOK 0x2
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#define TZC_ACTION_RV_HIGHERR 0x3
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/* Used along with 'tzc_region_attributes_t' below */
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#define TZC_REGION_ATTR_S_RD_SHIFT 30
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#define TZC_REGION_ATTR_S_WR_SHIFT 31
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#define TZC_REGION_ATTR_F_EN_SHIFT 0
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#define TZC_REGION_ATTR_SEC_SHIFT 30
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#define TZC_REGION_ATTR_S_RD_MASK 0x1
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#define TZC_REGION_ATTR_S_WR_MASK 0x1
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#define TZC_REGION_ATTR_SEC_MASK 0x3
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#define TZC_REGION_ACCESS_WR_EN_SHIFT 16
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#define TZC_REGION_ACCESS_RD_EN_SHIFT 0
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#define TZC_REGION_ACCESS_ID_MASK 0xf
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/* Macros for allowing Non-Secure access to a region based on NSAID */
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#define TZC_REGION_ACCESS_RD(nsaid) \
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((1 << (nsaid & TZC_REGION_ACCESS_ID_MASK)) << \
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TZC_REGION_ACCESS_RD_EN_SHIFT)
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#define TZC_REGION_ACCESS_WR(nsaid) \
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((1 << (nsaid & TZC_REGION_ACCESS_ID_MASK)) << \
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TZC_REGION_ACCESS_WR_EN_SHIFT)
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#define TZC_REGION_ACCESS_RDWR(nsaid) \
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(TZC_REGION_ACCESS_RD(nsaid) | \
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TZC_REGION_ACCESS_WR(nsaid))
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#ifndef __ASSEMBLY__
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/* Returns offset of registers to program for a given region no */
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#define TZC_REGION_OFFSET(region_size, region_no) \
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((region_size) * (region_no))
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/*
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* What type of action is expected when an access violation occurs.
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* The memory requested is returned as zero. But we can also raise an event to
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* let the system know it happened.
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* We can raise an interrupt(INT) and/or cause an exception(ERR).
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* TZC_ACTION_NONE - No interrupt, no Exception
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* TZC_ACTION_ERR - No interrupt, raise exception -> sync external
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* data abort
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* TZC_ACTION_INT - Raise interrupt, no exception
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* TZC_ACTION_ERR_INT - Raise interrupt, raise exception -> sync
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* external data abort
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*/
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typedef enum {
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TZC_ACTION_NONE = 0,
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TZC_ACTION_ERR = 1,
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TZC_ACTION_INT = 2,
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TZC_ACTION_ERR_INT = (TZC_ACTION_ERR | TZC_ACTION_INT)
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} tzc_action_t;
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/*
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* Controls secure access to a region. If not enabled secure access is not
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* allowed to region.
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*/
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typedef enum {
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TZC_REGION_S_NONE = 0,
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TZC_REGION_S_RD = 1,
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TZC_REGION_S_WR = 2,
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TZC_REGION_S_RDWR = (TZC_REGION_S_RD | TZC_REGION_S_WR)
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} tzc_region_attributes_t;
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#endif /* __ASSEMBLY__ */
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#endif /* __TZC_COMMON_H__ */
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