89 lines
2.3 KiB
C
89 lines
2.3 KiB
C
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/*
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* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef __PLATFORM_DEF_H__
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#define __PLATFORM_DEF_H__
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#include <arch.h>
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#include <common_def.h>
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#include <tbbr/tbbr_img_def.h>
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#include "hi3798cv200.h"
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#include "poplar_layout.h" /* BL memory region sizes, etc */
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#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64"
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#define PLATFORM_LINKER_ARCH aarch64
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#define PLAT_ARM_CRASH_UART_BASE PL011_UART0_BASE
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#define PLAT_ARM_CRASH_UART_CLK_IN_HZ PL011_UART0_CLK_IN_HZ
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#define ARM_CONSOLE_BAUDRATE PL011_BAUDRATE
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/* Generic platform constants */
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#define PLATFORM_STACK_SIZE (0x800)
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#define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n"
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#define BOOT_EMMC_NAME "l-loader.bin"
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#define PLATFORM_CACHE_LINE_SIZE (64)
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#define PLATFORM_CLUSTER_COUNT (1)
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#define PLATFORM_CORE_COUNT (4)
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#define PLATFORM_MAX_CPUS_PER_CLUSTER (4)
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/* IO framework user */
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#define MAX_IO_DEVICES (4)
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#define MAX_IO_HANDLES (4)
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#define MAX_IO_BLOCK_DEVICES (2)
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/* Memory map related constants */
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#define DDR_BASE (0x00000000)
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#define DDR_SIZE (0x40000000)
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#define DEVICE_BASE (0xF0000000)
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#define DEVICE_SIZE (0x0F000000)
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#define TEE_SEC_MEM_BASE (0x70000000)
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#define TEE_SEC_MEM_SIZE (0x10000000)
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#define BL_MEM_BASE (BL1_RO_BASE)
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#define BL_MEM_LIMIT (BL31_LIMIT)
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#define BL_MEM_SIZE (BL_MEM_LIMIT - BL_MEM_BASE)
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#define PLAT_ARM_NS_IMAGE_OFFSET 0x37000000
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/* Page table and MMU setup constants */
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#define ADDR_SPACE_SIZE (1ull << 32)
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#define MAX_XLAT_TABLES (4)
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#define MAX_MMAP_REGIONS (16)
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#define CACHE_WRITEBACK_SHIFT (6)
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#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT)
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/* Power states */
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#define PLAT_MAX_PWR_LVL (MPIDR_AFFLVL1)
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#define PLAT_MAX_OFF_STATE 2
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#define PLAT_MAX_RET_STATE 1
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/* Interrupt controller */
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#define PLAT_ARM_GICD_BASE GICD_BASE
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#define PLAT_ARM_GICC_BASE GICC_BASE
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#define PLAT_ARM_G1S_IRQS HISI_IRQ_SEC_SGI_0, \
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HISI_IRQ_SEC_SGI_1, \
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HISI_IRQ_SEC_SGI_2, \
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HISI_IRQ_SEC_SGI_3, \
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HISI_IRQ_SEC_SGI_4, \
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HISI_IRQ_SEC_SGI_5, \
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HISI_IRQ_SEC_SGI_6, \
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HISI_IRQ_SEC_SGI_7, \
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HISI_IRQ_SEC_TIMER0, \
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HISI_IRQ_SEC_TIMER1, \
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HISI_IRQ_SEC_TIMER2, \
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HISI_IRQ_SEC_TIMER3, \
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HISI_IRQ_SEC_AXI
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#define PLAT_ARM_G0_IRQS
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#endif /* __PLATFORM_DEF_H__ */
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