2017-08-12 10:07:39 +01:00
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/*
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2020-12-14 03:26:36 +00:00
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* Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
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2017-08-12 10:07:39 +01:00
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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2018-07-20 09:17:26 +01:00
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#ifndef PLATFORM_DEF_H
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#define PLATFORM_DEF_H
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2017-08-12 10:07:39 +01:00
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2018-12-14 00:18:21 +00:00
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#include <common/tbbr/tbbr_img_def.h>
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#include <lib/utils_def.h>
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#include <plat/common/common_def.h>
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2017-08-12 10:07:39 +01:00
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#include <sunxi_mmap.h>
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2020-11-28 01:38:15 +00:00
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#ifdef SUNXI_BL31_IN_DRAM
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2020-11-28 01:39:17 +00:00
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#define BL31_BASE SUNXI_DRAM_BASE
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#define BL31_LIMIT (SUNXI_DRAM_BASE + 0x40000)
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#define MAX_XLAT_TABLES 4
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#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
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#define SUNXI_BL33_VIRT_BASE PRELOADED_BL33_BASE
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2020-11-28 01:38:15 +00:00
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#else /* !SUNXI_BL31_IN_DRAM */
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2021-07-23 04:35:24 +01:00
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#define BL31_BASE (SUNXI_SRAM_A2_BASE + \
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SUNXI_SRAM_A2_BL31_OFFSET)
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2019-12-29 18:22:55 +00:00
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#define BL31_LIMIT (SUNXI_SRAM_A2_BASE + \
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SUNXI_SRAM_A2_SIZE - SUNXI_SCP_SIZE)
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2017-08-12 10:07:39 +01:00
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2019-10-27 19:07:52 +00:00
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/* Overwrite U-Boot SPL, but reserve the first page for the SPL header. */
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#define BL31_NOBITS_BASE (SUNXI_SRAM_A1_BASE + 0x1000)
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#define BL31_NOBITS_LIMIT (SUNXI_SRAM_A1_BASE + SUNXI_SRAM_A1_SIZE)
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2020-11-28 01:38:15 +00:00
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#define MAX_XLAT_TABLES 1
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#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 28)
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2020-12-14 02:22:42 +00:00
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#define SUNXI_BL33_VIRT_BASE SUNXI_DRAM_VIRT_BASE
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2020-11-28 01:38:15 +00:00
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2021-04-04 21:54:17 +01:00
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/* The SCP firmware is allocated the last 16KiB of SRAM A2. */
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#define SUNXI_SCP_BASE BL31_LIMIT
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#define SUNXI_SCP_SIZE 0x4000
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2020-12-14 02:22:42 +00:00
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#endif /* SUNXI_BL31_IN_DRAM */
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2018-09-20 21:13:55 +01:00
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2018-09-16 02:08:06 +01:00
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/* How much DRAM to map (to map BL33, for fetching the DTB from U-Boot) */
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2018-09-20 21:13:55 +01:00
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#define SUNXI_DRAM_MAP_SIZE (64U << 20)
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2017-08-12 10:07:39 +01:00
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#define CACHE_WRITEBACK_SHIFT 6
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#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT)
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2020-12-14 02:22:42 +00:00
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#define MAX_STATIC_MMAP_REGIONS 3
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2020-12-14 02:45:49 +00:00
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#define MAX_MMAP_REGIONS (5 + MAX_STATIC_MMAP_REGIONS)
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2017-08-12 10:07:39 +01:00
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2018-10-21 18:41:03 +01:00
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#define PLAT_CSS_SCP_COM_SHARED_MEM_BASE \
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(SUNXI_SRAM_A2_BASE + SUNXI_SRAM_A2_SIZE - 0x200)
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2018-07-20 09:17:26 +01:00
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#define PLAT_MAX_PWR_LVL_STATES U(2)
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#define PLAT_MAX_RET_STATE U(1)
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#define PLAT_MAX_OFF_STATE U(2)
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2017-08-12 10:07:39 +01:00
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2018-07-20 09:17:26 +01:00
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#define PLAT_MAX_PWR_LVL U(2)
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2019-12-13 16:48:27 +00:00
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#define PLAT_NUM_PWR_DOMAINS (U(1) + \
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2017-08-12 10:07:39 +01:00
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PLATFORM_CLUSTER_COUNT + \
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PLATFORM_CORE_COUNT)
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#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
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2019-12-13 16:48:27 +00:00
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#define PLATFORM_CLUSTER_COUNT U(1)
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2017-08-12 10:07:39 +01:00
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#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER_COUNT * \
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PLATFORM_MAX_CPUS_PER_CLUSTER)
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2019-12-13 16:48:27 +00:00
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#define PLATFORM_MAX_CPUS_PER_CLUSTER U(4)
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2017-08-12 10:07:39 +01:00
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#define PLATFORM_STACK_SIZE (0x1000 / PLATFORM_CORE_COUNT)
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2018-06-19 20:14:50 +01:00
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#ifndef SPD_none
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#ifndef BL32_BASE
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#define BL32_BASE SUNXI_DRAM_BASE
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#endif
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#endif
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2018-07-20 09:17:26 +01:00
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#endif /* PLATFORM_DEF_H */
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