2017-05-24 01:45:05 +01:00
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/*
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* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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2018-11-08 10:20:19 +00:00
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#ifndef HI6220_REGS_PIN_H
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#define HI6220_REGS_PIN_H
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2017-05-24 01:45:05 +01:00
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#define IOMG_BASE 0xF7010000
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#define IOMG_SD_CLK (IOMG_BASE + 0x0C)
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#define IOMG_SD_CMD (IOMG_BASE + 0x10)
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#define IOMG_SD_DATA0 (IOMG_BASE + 0x14)
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#define IOMG_SD_DATA1 (IOMG_BASE + 0x18)
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#define IOMG_SD_DATA2 (IOMG_BASE + 0x1C)
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#define IOMG_SD_DATA3 (IOMG_BASE + 0x20)
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#define IOMG_GPIO24 (IOMG_BASE + 0x140)
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#define IOMG_MUX_FUNC0 0
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#define IOMG_MUX_FUNC1 1
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#define IOMG_MUX_FUNC2 2
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#define IOCG1_BASE 0xF7010800
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#define IOCG2_BASE 0xF8001800
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#define IOCG_SD_CLK (IOCG1_BASE + 0x0C)
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#define IOCG_SD_CMD (IOCG1_BASE + 0x10)
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#define IOCG_SD_DATA0 (IOCG1_BASE + 0x14)
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#define IOCG_SD_DATA1 (IOCG1_BASE + 0x18)
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#define IOCG_SD_DATA2 (IOCG1_BASE + 0x1C)
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#define IOCG_SD_DATA3 (IOCG1_BASE + 0x20)
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#define IOCG_GPIO24 (IOCG1_BASE + 0x150)
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#define IOCG_GPIO8 (IOCG2_BASE + 0x30)
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#define IOCG_DRIVE_8MA (2 << 4)
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#define IOCG_DRIVE_10MA (3 << 4)
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#define IOCG_INPUT_16MA 0x64
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#define IOCG_INPUT_12MA 0x54
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#define IOCG_PULLDOWN (1 << 1)
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#define IOCG_PULLUP (1 << 0)
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2018-11-08 10:20:19 +00:00
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#endif /* HI6220_REGS_PIN_H */
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