2016-03-18 20:07:33 +00:00
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/*
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2019-01-11 22:48:41 +00:00
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* Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
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2018-08-03 11:18:15 +01:00
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* Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
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2016-03-18 20:07:33 +00:00
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*
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2017-05-03 09:38:09 +01:00
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* SPDX-License-Identifier: BSD-3-Clause
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2016-03-18 20:07:33 +00:00
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*/
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#include <arch.h>
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#include <asm_macros.S>
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2019-01-11 22:48:41 +00:00
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#include <common/bl_common.h>
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2016-03-18 20:07:33 +00:00
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#include <memctrl_v2.h>
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2018-12-14 00:18:21 +00:00
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#include <plat/common/common_def.h>
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2016-03-18 20:07:33 +00:00
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#include <tegra_def.h>
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2018-08-03 11:18:15 +01:00
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#define TEGRA186_MC_CTX_SIZE 0x93
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2016-03-18 20:07:33 +00:00
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2018-11-09 17:08:16 +00:00
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.globl tegra186_get_mc_ctx_size
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2016-03-18 20:07:33 +00:00
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/*
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2018-11-09 17:08:16 +00:00
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* Tegra186 reset data (offset 0x0 - 0x420)
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2016-03-18 20:07:33 +00:00
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*
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2018-11-09 17:08:16 +00:00
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* 0x000: MC context start
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* 0x420: MC context end
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2016-03-18 20:07:33 +00:00
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*/
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.align 4
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2018-08-03 11:18:15 +01:00
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__tegra186_mc_context:
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.rept TEGRA186_MC_CTX_SIZE
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2016-03-18 20:07:33 +00:00
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.quad 0
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.endr
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.align 4
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2018-11-09 17:08:16 +00:00
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__tegra186_mc_context_end:
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2017-11-08 22:45:08 +00:00
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2018-08-03 11:18:15 +01:00
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/* return the size of the MC context */
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2018-11-09 17:08:16 +00:00
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func tegra186_get_mc_ctx_size
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adr x0, __tegra186_mc_context_end
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adr x1, __tegra186_mc_context
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2017-11-08 22:45:08 +00:00
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sub x0, x0, x1
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ret
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2018-11-09 17:08:16 +00:00
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endfunc tegra186_get_mc_ctx_size
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