92 lines
3.7 KiB
Markdown
92 lines
3.7 KiB
Markdown
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ARM SiP Service
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===============
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This document enumerates and describes the ARM SiP (Silicon Provider) services.
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SiP services are non-standard, platform-specific services offered by the silicon
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implementer or platform provider. They are accessed via. `SMC` ("SMC calls")
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instruction executed from Exception Levels below EL3. SMC calls for SiP
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services:
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* Follow [SMC Calling Convention][SMCCC];
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* Use SMC function IDs that fall in the SiP range, which are `0xc2000000` -
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`0xc200ffff` for 64-bit calls, and `0x82000000` - `0x8200ffff` for 32-bit
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calls.
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The ARM SiP implementation offers the following services:
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* Performance Measurement Framework (PMF)
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* Execution State Switching service
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Source definitions for ARM SiP service are located in the `arm_sip_svc.h` header
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file.
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Performance Measurement Framework (PMF)
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---------------------------------------
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The [Performance Measurement Framework](./firmware-design.md#13--performance-measurement-framework)
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allows callers to retrieve timestamps captured at various paths in ARM Trusted
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Firmware execution. It's described in detail in [Firmware Design document][Firmware Design].
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Execution State Switching service
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---------------------------------
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Execution State Switching service provides a mechanism for a non-secure lower
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Exception Level (either EL2, or NS EL1 if EL2 isn't implemented) to request to
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switch its execution state (a.k.a. Register Width), either from AArch64 to
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AArch32, or from AArch32 to AArch64, for the calling CPU. This service is only
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available when ARM Trusted Firmware is built for AArch64 (i.e. when build option
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`ARCH` is set to `aarch64`).
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### `ARM_SIP_SVC_EXE_STATE_SWITCH`
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Arguments:
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uint32_t Function ID
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uint32_t PC hi
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uint32_t PC lo
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uint32_t Cookie hi
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uint32_t Cookie lo
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Return:
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uint32_t
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The function ID parameter must be `0x82000020`. It uniquely identifies the
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Execution State Switching service being requested.
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The parameters _PC hi_ and _PC lo_ defines upper and lower words, respectively,
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of the entry point (physical address) at which execution should start, after
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Execution State has been switched. When calling from AArch64, _PC hi_ must be 0.
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When execution starts at the supplied entry point after Execution State has been
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switched, the parameters _Cookie hi_ and _Cookie lo_ are passed in CPU registers
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0 and 1, respectively. When calling from AArch64, _Cookie hi_ must be 0.
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This call can only be made on the primary CPU, before any secondaries were
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brought up with `CPU_ON` PSCI call. Otherwise, the call will always fail.
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The effect of switching execution state is as if the Exception Level were
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entered for the first time, following power on. This means CPU registers that
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have a defined reset value by the Architecture will assume that value. Other
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registers should not be expected to hold their values before the call was made.
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CPU endianness, however, is preserved from the previous execution state. Note
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that this switches the execution state of the calling CPU only. This is not a
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substitute for PSCI `SYSTEM_RESET`.
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The service may return the following error codes:
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- `STATE_SW_E_PARAM`: If any of the parameters were deemed invalid for
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a specific request.
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- `STATE_SW_E_DENIED`: If the call is not successful, or when ARM Trusted
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Firmware is built for AArch32.
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If the call is successful, the caller wouldn't observe the SMC returning.
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Instead, execution starts at the supplied entry point, with the CPU registers 0
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and 1 populated with the supplied _Cookie hi_ and _Cookie lo_ values,
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respectively.
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- - - - - - - - - - - - - - - - - - - - - - - - - -
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[Firmware Design]: ./firmware-design.md
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[SMCCC]: http://infocenter.arm.com/help/topic/com.arm.doc.den0028a/index.html "SMC Calling Convention PDD (ARM DEN 0028A)"
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