2015-09-03 14:18:02 +01:00
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/*
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* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <arch.h>
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#include <arch_helpers.h>
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#include <assert.h>
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#include <debug.h>
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#include <gic_common.h>
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#include <gicv3.h>
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#include "gicv3_private.h"
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static const gicv3_driver_data_t *driver_data;
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static unsigned int gicv2_compat;
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/*******************************************************************************
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* This function initialises the ARM GICv3 driver in EL3 with provided platform
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* inputs.
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******************************************************************************/
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void gicv3_driver_init(const gicv3_driver_data_t *plat_driver_data)
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{
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unsigned int gic_version;
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assert(plat_driver_data);
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assert(plat_driver_data->gicd_base);
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assert(plat_driver_data->gicr_base);
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assert(plat_driver_data->rdistif_num);
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assert(plat_driver_data->rdistif_base_addrs);
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assert(IS_IN_EL3());
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/*
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* The platform should provide a list of at least one type of
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* interrupts
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*/
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assert(plat_driver_data->g0_interrupt_array ||
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plat_driver_data->g1s_interrupt_array);
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/*
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* If there are no interrupts of a particular type, then the number of
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* interrupts of that type should be 0 and vice-versa.
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*/
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assert(plat_driver_data->g0_interrupt_array ?
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plat_driver_data->g0_interrupt_num :
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plat_driver_data->g0_interrupt_num == 0);
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assert(plat_driver_data->g1s_interrupt_array ?
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plat_driver_data->g1s_interrupt_num :
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plat_driver_data->g1s_interrupt_num == 0);
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/* Check for system register support */
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assert(read_id_aa64pfr0_el1() &
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(ID_AA64PFR0_GIC_MASK << ID_AA64PFR0_GIC_SHIFT));
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/* The GIC version should be 3.0 */
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gic_version = gicd_read_pidr2(plat_driver_data->gicd_base);
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gic_version >>= PIDR2_ARCH_REV_SHIFT;
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gic_version &= PIDR2_ARCH_REV_MASK;
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assert(gic_version == ARCH_REV_GICV3);
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/*
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* Find out whether the GIC supports the GICv2 compatibility mode. The
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* ARE_S bit resets to 0 if supported
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*/
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gicv2_compat = gicd_read_ctlr(plat_driver_data->gicd_base);
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gicv2_compat >>= CTLR_ARE_S_SHIFT;
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gicv2_compat = !(gicv2_compat & CTLR_ARE_S_MASK);
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/*
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* Find the base address of each implemented Redistributor interface.
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* The number of interfaces should be equal to the number of CPUs in the
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* system. The memory for saving these addresses has to be allocated by
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* the platform port
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*/
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gicv3_rdistif_base_addrs_probe(plat_driver_data->rdistif_base_addrs,
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plat_driver_data->rdistif_num,
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plat_driver_data->gicr_base,
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plat_driver_data->mpidr_to_core_pos);
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driver_data = plat_driver_data;
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INFO("GICv3 %s legacy support detected."
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" ARM GICV3 driver initialized in EL3\n",
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gicv2_compat ? "with" : "without");
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}
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/*******************************************************************************
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* This function initialises the GIC distributor interface based upon the data
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* provided by the platform while initialising the driver.
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******************************************************************************/
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void gicv3_distif_init(void)
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{
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assert(driver_data);
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assert(driver_data->gicd_base);
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assert(driver_data->g1s_interrupt_array);
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assert(driver_data->g0_interrupt_array);
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assert(IS_IN_EL3());
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/*
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* Clear the "enable" bits for G0/G1S/G1NS interrupts before configuring
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* the ARE_S bit. The Distributor might generate a system error
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* otherwise.
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*/
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gicd_clr_ctlr(driver_data->gicd_base,
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CTLR_ENABLE_G0_BIT |
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CTLR_ENABLE_G1S_BIT |
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CTLR_ENABLE_G1NS_BIT,
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RWP_TRUE);
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/* Set the ARE_S and ARE_NS bit now that interrupts have been disabled */
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gicd_set_ctlr(driver_data->gicd_base,
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CTLR_ARE_S_BIT | CTLR_ARE_NS_BIT, RWP_TRUE);
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/* Set the default attribute of all SPIs */
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gicv3_spis_configure_defaults(driver_data->gicd_base);
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/* Configure the G1S SPIs */
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gicv3_secure_spis_configure(driver_data->gicd_base,
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driver_data->g1s_interrupt_num,
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driver_data->g1s_interrupt_array,
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2015-12-03 14:12:54 +00:00
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INTR_GROUP1S);
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2015-09-03 14:18:02 +01:00
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/* Configure the G0 SPIs */
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gicv3_secure_spis_configure(driver_data->gicd_base,
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driver_data->g0_interrupt_num,
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driver_data->g0_interrupt_array,
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2015-12-03 14:12:54 +00:00
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INTR_GROUP0);
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2015-09-03 14:18:02 +01:00
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/* Enable the secure SPIs now that they have been configured */
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gicd_set_ctlr(driver_data->gicd_base,
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CTLR_ENABLE_G1S_BIT | CTLR_ENABLE_G0_BIT,
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RWP_TRUE);
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}
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/*******************************************************************************
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* This function initialises the GIC Redistributor interface of the calling CPU
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* (identified by the 'proc_num' parameter) based upon the data provided by the
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* platform while initialising the driver.
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******************************************************************************/
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void gicv3_rdistif_init(unsigned int proc_num)
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{
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uintptr_t gicr_base;
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assert(driver_data);
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assert(proc_num < driver_data->rdistif_num);
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assert(driver_data->rdistif_base_addrs);
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assert(driver_data->gicd_base);
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assert(gicd_read_ctlr(driver_data->gicd_base) & CTLR_ARE_S_BIT);
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assert(driver_data->g1s_interrupt_array);
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assert(driver_data->g0_interrupt_array);
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assert(IS_IN_EL3());
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gicr_base = driver_data->rdistif_base_addrs[proc_num];
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/* Set the default attribute of all SGIs and PPIs */
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gicv3_ppi_sgi_configure_defaults(gicr_base);
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/* Configure the G1S SGIs/PPIs */
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gicv3_secure_ppi_sgi_configure(gicr_base,
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driver_data->g1s_interrupt_num,
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driver_data->g1s_interrupt_array,
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INTR_GROUP1S);
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/* Configure the G0 SGIs/PPIs */
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gicv3_secure_ppi_sgi_configure(gicr_base,
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driver_data->g0_interrupt_num,
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driver_data->g0_interrupt_array,
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INTR_GROUP0);
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2015-09-03 14:18:02 +01:00
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}
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/*******************************************************************************
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* This function enables the GIC CPU interface of the calling CPU using only
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* system register accesses.
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******************************************************************************/
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void gicv3_cpuif_enable(unsigned int proc_num)
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{
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uintptr_t gicr_base;
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unsigned int scr_el3;
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unsigned int icc_sre_el3;
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assert(driver_data);
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assert(proc_num < driver_data->rdistif_num);
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assert(driver_data->rdistif_base_addrs);
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assert(IS_IN_EL3());
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/* Mark the connected core as awake */
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gicr_base = driver_data->rdistif_base_addrs[proc_num];
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gicv3_rdistif_mark_core_awake(gicr_base);
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/* Disable the legacy interrupt bypass */
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icc_sre_el3 = ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT;
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/*
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* Enable system register access for EL3 and allow lower exception
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* levels to configure the same for themselves. If the legacy mode is
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* not supported, the SRE bit is RAO/WI
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*/
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icc_sre_el3 |= (ICC_SRE_EN_BIT | ICC_SRE_SRE_BIT);
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write_icc_sre_el3(read_icc_sre_el3() | icc_sre_el3);
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scr_el3 = read_scr_el3();
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/*
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* Switch to NS state to write Non secure ICC_SRE_EL1 and
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* ICC_SRE_EL2 registers.
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*/
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write_scr_el3(scr_el3 | SCR_NS_BIT);
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isb();
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write_icc_sre_el2(read_icc_sre_el2() | icc_sre_el3);
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write_icc_sre_el1(ICC_SRE_SRE_BIT);
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isb();
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/* Switch to secure state. */
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write_scr_el3(scr_el3 & (~SCR_NS_BIT));
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isb();
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/* Program the idle priority in the PMR */
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write_icc_pmr_el1(GIC_PRI_MASK);
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/* Enable Group0 interrupts */
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write_icc_igrpen0_el1(IGRPEN1_EL1_ENABLE_G0_BIT);
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/* Enable Group1 Secure interrupts */
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write_icc_igrpen1_el3(read_icc_igrpen1_el3() |
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IGRPEN1_EL3_ENABLE_G1S_BIT);
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/* Write the secure ICC_SRE_EL1 register */
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write_icc_sre_el1(ICC_SRE_SRE_BIT);
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isb();
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}
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/*******************************************************************************
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* This function disables the GIC CPU interface of the calling CPU using
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* only system register accesses.
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******************************************************************************/
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void gicv3_cpuif_disable(unsigned int proc_num)
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{
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uintptr_t gicr_base;
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assert(driver_data);
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assert(proc_num < driver_data->rdistif_num);
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assert(driver_data->rdistif_base_addrs);
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assert(IS_IN_EL3());
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/* Disable legacy interrupt bypass */
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write_icc_sre_el3(read_icc_sre_el3() |
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(ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT));
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/* Disable Group0 interrupts */
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write_icc_igrpen0_el1(read_icc_igrpen0_el1() &
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~IGRPEN1_EL1_ENABLE_G0_BIT);
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/* Disable Group1 Secure interrupts */
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write_icc_igrpen1_el3(read_icc_igrpen1_el3() &
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~IGRPEN1_EL3_ENABLE_G1S_BIT);
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/* Synchronise accesses to group enable registers */
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isb();
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/* Mark the connected core as asleep */
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gicr_base = driver_data->rdistif_base_addrs[proc_num];
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gicv3_rdistif_mark_core_asleep(gicr_base);
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}
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/*******************************************************************************
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* This function returns the id of the highest priority pending interrupt at
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* the GIC cpu interface.
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******************************************************************************/
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unsigned int gicv3_get_pending_interrupt_id(void)
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{
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unsigned int id;
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assert(IS_IN_EL3());
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id = read_icc_hppir0_el1() & HPPIR0_EL1_INTID_MASK;
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/*
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* If the ID is special identifier corresponding to G1S or G1NS
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* interrupt, then read the highest pending group 1 interrupt.
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*/
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if ((id == PENDING_G1S_INTID) || (id == PENDING_G1NS_INTID))
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return read_icc_hppir1_el1() & HPPIR1_EL1_INTID_MASK;
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return id;
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}
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/*******************************************************************************
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* This function returns the type of the highest priority pending interrupt at
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* the GIC cpu interface. The return values can be one of the following :
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* PENDING_G1S_INTID : The interrupt type is secure Group 1.
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* PENDING_G1NS_INTID : The interrupt type is non secure Group 1.
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* 0 - 1019 : The interrupt type is secure Group 0.
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* GIC_SPURIOUS_INTERRUPT : there is no pending interrupt with
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* sufficient priority to be signaled
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******************************************************************************/
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unsigned int gicv3_get_pending_interrupt_type(void)
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{
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assert(IS_IN_EL3());
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return read_icc_hppir0_el1() & HPPIR0_EL1_INTID_MASK;
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}
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/*******************************************************************************
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* This function returns the type of the interrupt id depending upon the group
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* this interrupt has been configured under by the interrupt controller i.e.
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* group0 or group1 Secure / Non Secure. The return value can be one of the
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* following :
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2015-12-03 14:12:54 +00:00
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* INTR_GROUP0 : The interrupt type is a Secure Group 0 interrupt
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* INTR_GROUP1S : The interrupt type is a Secure Group 1 secure interrupt
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* INTR_GROUP1NS: The interrupt type is a Secure Group 1 non secure
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2015-09-03 14:18:02 +01:00
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* interrupt.
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******************************************************************************/
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unsigned int gicv3_get_interrupt_type(unsigned int id,
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unsigned int proc_num)
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{
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unsigned int igroup, grpmodr;
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uintptr_t gicr_base;
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assert(IS_IN_EL3());
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assert(driver_data);
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/* Ensure the parameters are valid */
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assert(id < PENDING_G1S_INTID || id >= MIN_LPI_ID);
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assert(proc_num < driver_data->rdistif_num);
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/* All LPI interrupts are Group 1 non secure */
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if (id >= MIN_LPI_ID)
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2015-12-03 14:12:54 +00:00
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return INTR_GROUP1NS;
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2015-09-03 14:18:02 +01:00
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if (id < MIN_SPI_ID) {
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assert(driver_data->rdistif_base_addrs);
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gicr_base = driver_data->rdistif_base_addrs[proc_num];
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igroup = gicr_get_igroupr0(gicr_base, id);
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grpmodr = gicr_get_igrpmodr0(gicr_base, id);
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} else {
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assert(driver_data->gicd_base);
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igroup = gicd_get_igroupr(driver_data->gicd_base, id);
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grpmodr = gicd_get_igrpmodr(driver_data->gicd_base, id);
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}
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/*
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* If the IGROUP bit is set, then it is a Group 1 Non secure
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* interrupt
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*/
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if (igroup)
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2015-12-03 14:12:54 +00:00
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return INTR_GROUP1NS;
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2015-09-03 14:18:02 +01:00
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/* If the GRPMOD bit is set, then it is a Group 1 Secure interrupt */
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if (grpmodr)
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2015-12-03 14:12:54 +00:00
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return INTR_GROUP1S;
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2015-09-03 14:18:02 +01:00
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/* Else it is a Group 0 Secure interrupt */
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2015-12-03 14:12:54 +00:00
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return INTR_GROUP0;
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2015-09-03 14:18:02 +01:00
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}
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