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arm-trusted-firmware/lib/cpus/aarch64/neoverse_n1.S

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Add support for Cortex-Ares and Cortex-A76 CPUs Both Cortex-Ares and Cortex-A76 CPUs use the ARM DynamIQ Shared Unit (DSU). The power-down and power-up sequences are therefore mostly managed in hardware, and required software operations are simple. Change-Id: I3a9447b5bdbdbc5ed845b20f6564d086516fa161 Signed-off-by: Isla Mitchell <isla.mitchell@arm.com>
2017-08-03 16:04:46 +01:00
/*
fix(security): workaround for CVE-2022-23960 Implements the loop workaround for Cortex-A77, Cortex-A78, Cortex-A710, Cortex-X2, Neoverse N1, Neoverse N2 and Neoverse V1 CPUs. Signed-off-by: Bipin Ravi <bipin.ravi@arm.com> Change-Id: I11d342df7a2068a15e18f4974c645af3b341235b
2022-01-18 07:59:06 +00:00
* Copyright (c) 2017-2022, Arm Limited and Contributors. All rights reserved.
Add support for Cortex-Ares and Cortex-A76 CPUs Both Cortex-Ares and Cortex-A76 CPUs use the ARM DynamIQ Shared Unit (DSU). The power-down and power-up sequences are therefore mostly managed in hardware, and required software operations are simple. Change-Id: I3a9447b5bdbdbc5ed845b20f6564d086516fa161 Signed-off-by: Isla Mitchell <isla.mitchell@arm.com>
2017-08-03 16:04:46 +01:00
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <arch.h>
#include <asm_macros.S>
Add AMU support for Cortex-Ares Change-Id: Ia170c12d3929a616ba80eb7645c301066641f5cc Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
2018-02-13 11:28:02 +00:00
#include <cpuamu.h>
Add support for Cortex-Ares and Cortex-A76 CPUs Both Cortex-Ares and Cortex-A76 CPUs use the ARM DynamIQ Shared Unit (DSU). The power-down and power-up sequences are therefore mostly managed in hardware, and required software operations are simple. Change-Id: I3a9447b5bdbdbc5ed845b20f6564d086516fa161 Signed-off-by: Isla Mitchell <isla.mitchell@arm.com>
2017-08-03 16:04:46 +01:00
#include <cpu_macros.S>
Add support for Neoverse-N2 CPUs. Enable basic support for Neoverse-N2 CPUs. Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com> Change-Id: I498adc2d9fc61ac6e1af8ece131039410872e8ad
2020-10-23 13:22:07 +01:00
#include <neoverse_n1.h>
fix(security): workaround for CVE-2022-23960 Implements the loop workaround for Cortex-A77, Cortex-A78, Cortex-A710, Cortex-X2, Neoverse N1, Neoverse N2 and Neoverse V1 CPUs. Signed-off-by: Bipin Ravi <bipin.ravi@arm.com> Change-Id: I11d342df7a2068a15e18f4974c645af3b341235b
2022-01-18 07:59:06 +00:00
#include "wa_cve_2022_23960_bhb_vector.S"
Add AMU support for Cortex-Ares Change-Id: Ia170c12d3929a616ba80eb7645c301066641f5cc Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
2018-02-13 11:28:02 +00:00
Add compile-time errors for HW_ASSISTED_COHERENCY flag This patch fixes this issue: https://github.com/ARM-software/tf-issues/issues/660 The introduced changes are the following: 1) Some cores implement cache coherency maintenance operation on the hardware level. For those cores, such as - but not only - the DynamIQ cores, it is mandatory that TF-A is compiled with the HW_ASSISTED_COHERENCY flag. If not, the core behaviour at runtime is unpredictable. To prevent this, compile time checks have been added and compilation errors are generated, if needed. 2) To enable this change for FVP, a logical separation has been done for the core libraries. A system cannot contain cores of both groups, i.e. cores that manage coherency on hardware and cores that don't do it. As such, depending on the HW_ASSISTED_COHERENCY flag, FVP includes the libraries only of the relevant cores. 3) The neoverse_e1.S file has been added to the FVP sources. Change-Id: I787d15819b2add4ec0d238249e04bf0497dc12f3 Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
2019-03-19 17:20:52 +00:00
/* Hardware handled coherency */
#if HW_ASSISTED_COHERENCY == 0
#error "Neoverse N1 must be compiled with HW_ASSISTED_COHERENCY enabled"
#endif
Apply compile-time check for AArch64-only cores Some cores support only AArch64 mode. In those cores, only a limited subset of the AArch32 system registers are implemented. Hence, if TF-A is supposed to run on AArch64-only cores, it must be compiled with CTX_INCLUDE_AARCH32_REGS=0. Currently, the default settings for compiling TF-A are with the AArch32 system registers included. So, if we compile TF-A the default way and attempt to run it on an AArch64-only core, we only get a runtime panic. Now a compile-time check has been added to ensure that this flag has the appropriate value when AArch64-only cores are included in the build. Change-Id: I298ec550037fafc9347baafb056926d149197d4c Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
2019-06-03 13:54:30 +01:00
/* 64-bit only core */
#if CTX_INCLUDE_AARCH32_REGS == 1
#error "Neoverse-N1 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
#endif
Neoverse N1 Errata Workaround 1542419 Coherent I-cache is causing a prefetch violation where when the core executes an instruction that has recently been modified, the core might fetch a stale instruction which violates the ordering of instruction fetches. The workaround includes an instruction sequence to implementation defined registers to trap all EL0 IC IVAU instructions to EL3 and a trap handler to execute a TLB inner-shareable invalidation to an arbitrary address followed by a DSB. Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com> Change-Id: Ic3b7cbb11cf2eaf9005523ef5578a372593ae4d6
2019-08-20 21:51:24 +01:00
.global neoverse_n1_errata_ic_trap_handler
fix(security): workaround for CVE-2022-23960 Implements the loop workaround for Cortex-A77, Cortex-A78, Cortex-A710, Cortex-X2, Neoverse N1, Neoverse N2 and Neoverse V1 CPUs. Signed-off-by: Bipin Ravi <bipin.ravi@arm.com> Change-Id: I11d342df7a2068a15e18f4974c645af3b341235b
2022-01-18 07:59:06 +00:00
#if WORKAROUND_CVE_2022_23960
wa_cve_2022_23960_bhb_vector_table NEOVERSE_N1_BHB_LOOP_COUNT, neoverse_n1
#endif /* WORKAROUND_CVE_2022_23960 */
Implement Cortex-Ares 1043202 erratum workaround The workaround uses the instruction patching feature of the Ares cpu. Change-Id: I868fce0dc0e8e41853dcce311f01ee3867aabb59 Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
2018-03-26 16:46:01 +01:00
/* --------------------------------------------------
Neoverse N1: Introduce workaround for Neoverse N1 erratum 1315703 Neoverse N1 erratum 1315703 is a Cat A (rare) erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set a bit in the implementation defined CPUACTLR2_EL1 system register, which will disable the load-bypass-store feature. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdocpjdoc-466751330-1032/index.html Change-Id: I5c708dbe0efa4daa0bcb6bd9622c5efe19c03af9 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2019-05-20 14:57:06 +01:00
* Errata Workaround for Neoverse N1 Erratum 1043202.
Rename Cortex-Ares to Neoverse N1 Change-Id: Ideb49011da35f39ff1959be6f5015fa212ca2b6b Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
2019-02-19 13:49:06 +00:00
* This applies to revision r0p0 and r1p0 of Neoverse N1.
Implement Cortex-Ares 1043202 erratum workaround The workaround uses the instruction patching feature of the Ares cpu. Change-Id: I868fce0dc0e8e41853dcce311f01ee3867aabb59 Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
2018-03-26 16:46:01 +01:00
* Inputs:
* x0: variant[4:7] and revision[0:3] of current cpu.
* Shall clobber: x0-x17
* --------------------------------------------------
*/
Rename Cortex-Ares to Neoverse N1 Change-Id: Ideb49011da35f39ff1959be6f5015fa212ca2b6b Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
2019-02-19 13:49:06 +00:00
func errata_n1_1043202_wa
Implement Cortex-Ares 1043202 erratum workaround The workaround uses the instruction patching feature of the Ares cpu. Change-Id: I868fce0dc0e8e41853dcce311f01ee3867aabb59 Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
2018-03-26 16:46:01 +01:00
/* Compare x0 against revision r1p0 */
mov x17, x30
bl check_errata_1043202
cbz x0, 1f
/* Apply instruction patching sequence */
ldr x0, =0x0
msr CPUPSELR_EL3, x0
ldr x0, =0xF3BF8F2F
msr CPUPOR_EL3, x0
ldr x0, =0xFFFFFFFF
msr CPUPMR_EL3, x0
ldr x0, =0x800200071
msr CPUPCR_EL3, x0
Fix for N1 1043202 Errata Workaround ISB instruction was removed from the N1 1043202 Errata Workaround [1], this fix is adding the ISB instruction back in. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com> Change-Id: I74eac7f6ad38991c36d423ad6aa44558033ad388
2019-08-19 17:06:18 +01:00
isb
Implement Cortex-Ares 1043202 erratum workaround The workaround uses the instruction patching feature of the Ares cpu. Change-Id: I868fce0dc0e8e41853dcce311f01ee3867aabb59 Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
2018-03-26 16:46:01 +01:00
1:
ret x17
Rename Cortex-Ares to Neoverse N1 Change-Id: Ideb49011da35f39ff1959be6f5015fa212ca2b6b Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
2019-02-19 13:49:06 +00:00
endfunc errata_n1_1043202_wa
Implement Cortex-Ares 1043202 erratum workaround The workaround uses the instruction patching feature of the Ares cpu. Change-Id: I868fce0dc0e8e41853dcce311f01ee3867aabb59 Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
2018-03-26 16:46:01 +01:00
func check_errata_1043202
/* Applies to r0p0 and r1p0 */
mov x1, #0x10
b cpu_rev_var_ls
endfunc check_errata_1043202
Disable speculative loads only if SSBS is supported Examine the ID_AA64PFR1_EL1 bits 7:4 to see if speculative loads (SSBS) is implemented, before disabling speculative loads. Change-Id: I7607c45ed2889260d22a94f6fd9af804520acf67 Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
2019-05-10 14:28:37 +01:00
/* --------------------------------------------------
* Disable speculative loads if Neoverse N1 supports
* SSBS.
*
* Shall clobber: x0.
* --------------------------------------------------
*/
func neoverse_n1_disable_speculative_loads
/* Check if the PE implements SSBS */
mrs x0, id_aa64pfr1_el1
tst x0, #(ID_AA64PFR1_EL1_SSBS_MASK << ID_AA64PFR1_EL1_SSBS_SHIFT)
b.eq 1f
/* Disable speculative loads */
msr SSBS, xzr
1:
ret
endfunc neoverse_n1_disable_speculative_loads
Workaround for Neoverse N1 erratum 1073348 Neoverse N1 erratum 1073348 is a Cat B erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set a bit in the implementation defined CPUACTLR_EL1 system register, which disables static prediction. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Change-Id: I674126c0af6e068eecb379a190bcf7c75dcbca8e Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
2019-06-24 17:23:50 +01:00
/* --------------------------------------------------
* Errata Workaround for Neoverse N1 Errata #1073348
* This applies to revision r0p0 and r1p0 of Neoverse N1.
* Inputs:
* x0: variant[4:7] and revision[0:3] of current cpu.
* Shall clobber: x0-x17
* --------------------------------------------------
*/
func errata_n1_1073348_wa
/* Compare x0 against revision r1p0 */
mov x17, x30
bl check_errata_1073348
cbz x0, 1f
mrs x1, NEOVERSE_N1_CPUACTLR_EL1
orr x1, x1, NEOVERSE_N1_CPUACTLR_EL1_BIT_6
msr NEOVERSE_N1_CPUACTLR_EL1, x1
1:
ret x17
endfunc errata_n1_1073348_wa
func check_errata_1073348
/* Applies to r0p0 and r1p0 */
mov x1, #0x10
b cpu_rev_var_ls
endfunc check_errata_1073348
Workaround for Neoverse N1 erratum 1130799 Neoverse N1 erratum 1130799 is a Cat B erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set a bit in the implementation defined CPUACTLR2_EL1 system register. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Change-Id: I252bc45f9733443ba0503fefe62f50fdea61da6d Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
2019-06-24 17:28:34 +01:00
/* --------------------------------------------------
* Errata Workaround for Neoverse N1 Errata #1130799
* This applies to revision <=r2p0 of Neoverse N1.
* Inputs:
* x0: variant[4:7] and revision[0:3] of current cpu.
* Shall clobber: x0-x17
* --------------------------------------------------
*/
func errata_n1_1130799_wa
/* Compare x0 against revision r2p0 */
mov x17, x30
bl check_errata_1130799
cbz x0, 1f
mrs x1, NEOVERSE_N1_CPUACTLR2_EL1
orr x1, x1, NEOVERSE_N1_CPUACTLR2_EL1_BIT_59
msr NEOVERSE_N1_CPUACTLR2_EL1, x1
1:
ret x17
endfunc errata_n1_1130799_wa
func check_errata_1130799
/* Applies to <=r2p0 */
mov x1, #0x20
b cpu_rev_var_ls
endfunc check_errata_1130799
Workaround for Neoverse N1 erratum 1165347 Neoverse N1 erratum 1165347 is a Cat B erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set two bits in the implementation defined CPUACTLR2_EL1 system register. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Change-Id: I163d0ea00578245c1323d2340314cdc3088c450d Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
2019-06-24 17:32:40 +01:00
/* --------------------------------------------------
* Errata Workaround for Neoverse N1 Errata #1165347
* This applies to revision <=r2p0 of Neoverse N1.
* Inputs:
* x0: variant[4:7] and revision[0:3] of current cpu.
* Shall clobber: x0-x17
* --------------------------------------------------
*/
func errata_n1_1165347_wa
/* Compare x0 against revision r2p0 */
mov x17, x30
bl check_errata_1165347
cbz x0, 1f
mrs x1, NEOVERSE_N1_CPUACTLR2_EL1
orr x1, x1, NEOVERSE_N1_CPUACTLR2_EL1_BIT_0
orr x1, x1, NEOVERSE_N1_CPUACTLR2_EL1_BIT_15
msr NEOVERSE_N1_CPUACTLR2_EL1, x1
1:
ret x17
endfunc errata_n1_1165347_wa
func check_errata_1165347
/* Applies to <=r2p0 */
mov x1, #0x20
b cpu_rev_var_ls
endfunc check_errata_1165347
Workaround for Neoverse N1 erratum 1207823 Neoverse N1 erratum 1207823 is a Cat B erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set a bit in the implementation defined CPUACTLR2_EL1 system register. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Change-Id: Ia932337821f1ef0d644db3612480462a8d924d21 Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
2019-06-24 17:35:37 +01:00
/* --------------------------------------------------
* Errata Workaround for Neoverse N1 Errata #1207823
* This applies to revision <=r2p0 of Neoverse N1.
* Inputs:
* x0: variant[4:7] and revision[0:3] of current cpu.
* Shall clobber: x0-x17
* --------------------------------------------------
*/
func errata_n1_1207823_wa
/* Compare x0 against revision r2p0 */
mov x17, x30
bl check_errata_1207823
cbz x0, 1f
mrs x1, NEOVERSE_N1_CPUACTLR2_EL1
orr x1, x1, NEOVERSE_N1_CPUACTLR2_EL1_BIT_11
msr NEOVERSE_N1_CPUACTLR2_EL1, x1
1:
ret x17
endfunc errata_n1_1207823_wa
func check_errata_1207823
/* Applies to <=r2p0 */
mov x1, #0x20
b cpu_rev_var_ls
endfunc check_errata_1207823
Workaround for Neoverse N1 erratum 1220197 Neoverse N1 erratum 1220197 is a Cat B erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set two bits in the implementation defined CPUECTLR_EL1 system register, which disables write streaming to the L2. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Change-Id: I9c3373f1b6d67d21ee71b2b80aec5e96826818e8 Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
2019-06-24 17:38:53 +01:00
/* --------------------------------------------------
* Errata Workaround for Neoverse N1 Errata #1220197
* This applies to revision <=r2p0 of Neoverse N1.
* Inputs:
* x0: variant[4:7] and revision[0:3] of current cpu.
* Shall clobber: x0-x17
* --------------------------------------------------
*/
func errata_n1_1220197_wa
/* Compare x0 against revision r2p0 */
mov x17, x30
bl check_errata_1220197
cbz x0, 1f
mrs x1, NEOVERSE_N1_CPUECTLR_EL1
orr x1, x1, NEOVERSE_N1_WS_THR_L2_MASK
msr NEOVERSE_N1_CPUECTLR_EL1, x1
1:
ret x17
endfunc errata_n1_1220197_wa
func check_errata_1220197
/* Applies to <=r2p0 */
mov x1, #0x20
b cpu_rev_var_ls
endfunc check_errata_1220197
Workaround for Neoverse N1 erratum 1257314 Neoverse N1 erratum 1257314 is a Cat B erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set a bit in the implementation defined CPUACTLR3_EL1 system register, which prevents parallel execution of divide and square root instructions. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Change-Id: I54f0f40ff9043efee40d51e796b92ed85b394cbb Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
2019-06-24 17:42:02 +01:00
/* --------------------------------------------------
* Errata Workaround for Neoverse N1 Errata #1257314
* This applies to revision <=r3p0 of Neoverse N1.
* Inputs:
* x0: variant[4:7] and revision[0:3] of current cpu.
* Shall clobber: x0-x17
* --------------------------------------------------
*/
func errata_n1_1257314_wa
/* Compare x0 against revision r3p0 */
mov x17, x30
bl check_errata_1257314
cbz x0, 1f
mrs x1, NEOVERSE_N1_CPUACTLR3_EL1
orr x1, x1, NEOVERSE_N1_CPUACTLR3_EL1_BIT_10
msr NEOVERSE_N1_CPUACTLR3_EL1, x1
1:
ret x17
endfunc errata_n1_1257314_wa
func check_errata_1257314
/* Applies to <=r3p0 */
mov x1, #0x30
b cpu_rev_var_ls
endfunc check_errata_1257314
Workaround for Neoverse N1 erratum 1262606 Neoverse N1 erratum 1262606 is a Cat B erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set a bit in the implementation defined CPUACTLR_EL1 system register, which delays instruction fetch after branch misprediction. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Change-Id: Idd980e9d5310232d38f0ce272862e1fb0f02ce9a Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
2019-06-24 17:44:58 +01:00
/* --------------------------------------------------
* Errata Workaround for Neoverse N1 Errata #1262606
* This applies to revision <=r3p0 of Neoverse N1.
* Inputs:
* x0: variant[4:7] and revision[0:3] of current cpu.
* Shall clobber: x0-x17
* --------------------------------------------------
*/
func errata_n1_1262606_wa
/* Compare x0 against revision r3p0 */
mov x17, x30
bl check_errata_1262606
cbz x0, 1f
mrs x1, NEOVERSE_N1_CPUACTLR_EL1
orr x1, x1, NEOVERSE_N1_CPUACTLR_EL1_BIT_13
msr NEOVERSE_N1_CPUACTLR_EL1, x1
1:
ret x17
endfunc errata_n1_1262606_wa
func check_errata_1262606
/* Applies to <=r3p0 */
mov x1, #0x30
b cpu_rev_var_ls
endfunc check_errata_1262606
Workaround for Neoverse N1 erratum 1262888 Neoverse N1 erratum 1262888 is a Cat B erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set a bit in the implementation defined CPUECTLR_EL1 system register, which disables the MMU hardware prefetcher. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Change-Id: Ib733d748e32a7ea6a2783f3d5a9c5e13eee01105 Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
2019-06-24 17:47:30 +01:00
/* --------------------------------------------------
* Errata Workaround for Neoverse N1 Errata #1262888
* This applies to revision <=r3p0 of Neoverse N1.
* Inputs:
* x0: variant[4:7] and revision[0:3] of current cpu.
* Shall clobber: x0-x17
* --------------------------------------------------
*/
func errata_n1_1262888_wa
/* Compare x0 against revision r3p0 */
mov x17, x30
bl check_errata_1262888
cbz x0, 1f
mrs x1, NEOVERSE_N1_CPUECTLR_EL1
orr x1, x1, NEOVERSE_N1_CPUECTLR_EL1_MM_TLBPF_DIS_BIT
msr NEOVERSE_N1_CPUECTLR_EL1, x1
1:
ret x17
endfunc errata_n1_1262888_wa
func check_errata_1262888
/* Applies to <=r3p0 */
mov x1, #0x30
b cpu_rev_var_ls
endfunc check_errata_1262888
Workaround for Neoverse N1 erratum 1275112 Neoverse N1 erratum 1275112 is a Cat B erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set a bit in the implementation defined CPUACTLR_EL1 system register, which delays instruction fetch after branch misprediction. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Change-Id: If7fe55fe92e656fa6aea12327ab297f2e6119833 Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
2019-06-24 17:49:01 +01:00
/* --------------------------------------------------
* Errata Workaround for Neoverse N1 Errata #1275112
* This applies to revision <=r3p0 of Neoverse N1.
* Inputs:
* x0: variant[4:7] and revision[0:3] of current cpu.
* Shall clobber: x0-x17
* --------------------------------------------------
*/
func errata_n1_1275112_wa
/* Compare x0 against revision r3p0 */
mov x17, x30
bl check_errata_1275112
cbz x0, 1f
mrs x1, NEOVERSE_N1_CPUACTLR_EL1
orr x1, x1, NEOVERSE_N1_CPUACTLR_EL1_BIT_13
msr NEOVERSE_N1_CPUACTLR_EL1, x1
1:
ret x17
endfunc errata_n1_1275112_wa
func check_errata_1275112
/* Applies to <=r3p0 */
mov x1, #0x30
b cpu_rev_var_ls
endfunc check_errata_1275112
Neoverse N1: Introduce workaround for Neoverse N1 erratum 1315703 Neoverse N1 erratum 1315703 is a Cat A (rare) erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set a bit in the implementation defined CPUACTLR2_EL1 system register, which will disable the load-bypass-store feature. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdocpjdoc-466751330-1032/index.html Change-Id: I5c708dbe0efa4daa0bcb6bd9622c5efe19c03af9 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2019-05-20 14:57:06 +01:00
/* --------------------------------------------------
* Errata Workaround for Neoverse N1 Erratum 1315703.
* This applies to revision <= r3p0 of Neoverse N1.
* Inputs:
* x0: variant[4:7] and revision[0:3] of current cpu.
* Shall clobber: x0-x17
* --------------------------------------------------
*/
func errata_n1_1315703_wa
/* Compare x0 against revision r3p1 */
mov x17, x30
bl check_errata_1315703
cbz x0, 1f
mrs x0, NEOVERSE_N1_CPUACTLR2_EL1
orr x0, x0, #NEOVERSE_N1_CPUACTLR2_EL1_BIT_16
msr NEOVERSE_N1_CPUACTLR2_EL1, x0
1:
ret x17
endfunc errata_n1_1315703_wa
func check_errata_1315703
/* Applies to everything <= r3p0. */
mov x1, #0x30
b cpu_rev_var_ls
endfunc check_errata_1315703
Neoverse N1 Errata Workaround 1542419 Coherent I-cache is causing a prefetch violation where when the core executes an instruction that has recently been modified, the core might fetch a stale instruction which violates the ordering of instruction fetches. The workaround includes an instruction sequence to implementation defined registers to trap all EL0 IC IVAU instructions to EL3 and a trap handler to execute a TLB inner-shareable invalidation to an arbitrary address followed by a DSB. Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com> Change-Id: Ic3b7cbb11cf2eaf9005523ef5578a372593ae4d6
2019-08-20 21:51:24 +01:00
/* --------------------------------------------------
* Errata Workaround for Neoverse N1 Erratum 1542419.
* This applies to revisions r3p0 - r4p0 of Neoverse N1
* Inputs:
* x0: variant[4:7] and revision[0:3] of current cpu.
* Shall clobber: x0-x17
* --------------------------------------------------
*/
func errata_n1_1542419_wa
/* Compare x0 against revision r3p0 and r4p0 */
mov x17, x30
bl check_errata_1542419
cbz x0, 1f
Fix white space errors + remove #if defined Fix a few white space errors and remove #if defined in workaround for N1 Errata 1542419. Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com> Change-Id: I07ac5a2fd50cd63de53c06e3d0f8262871b62fad
2019-10-11 21:45:24 +01:00
/* Apply instruction patching sequence */
Neoverse N1 Errata Workaround 1542419 Coherent I-cache is causing a prefetch violation where when the core executes an instruction that has recently been modified, the core might fetch a stale instruction which violates the ordering of instruction fetches. The workaround includes an instruction sequence to implementation defined registers to trap all EL0 IC IVAU instructions to EL3 and a trap handler to execute a TLB inner-shareable invalidation to an arbitrary address followed by a DSB. Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com> Change-Id: Ic3b7cbb11cf2eaf9005523ef5578a372593ae4d6
2019-08-20 21:51:24 +01:00
ldr x0, =0x0
msr CPUPSELR_EL3, x0
ldr x0, =0xEE670D35
msr CPUPOR_EL3, x0
ldr x0, =0xFFFF0FFF
msr CPUPMR_EL3, x0
ldr x0, =0x08000020007D
msr CPUPCR_EL3, x0
isb
1:
ret x17
endfunc errata_n1_1542419_wa
func check_errata_1542419
/* Applies to everything r3p0 - r4p0. */
mov x1, #0x30
mov x2, #0x40
b cpu_rev_var_range
endfunc check_errata_1542419
Workaround for Neoverse N1 erratum 1868343 Neoverse N1 erratum 1868343 is a Cat B erratum, present in older revisions of the Neoverse N1 processor core. The workaround is to set a bit in the CPUACTLR_EL1 system register, which delays instruction fetch after branch misprediction. This workaround will have a small impact on performance. SDEN can be found here: https://documentation-service.arm.com/static/5f2c130260a93e65927bc92f Signed-off-by: John Powell <john.powell@arm.com> Change-Id: I37da2b3b2da697701b883bff9a1eff2772352844
2020-08-05 18:27:12 +01:00
/* --------------------------------------------------
* Errata Workaround for Neoverse N1 Errata #1868343.
* This applies to revision <= r4p0 of Neoverse N1.
* This workaround is the same as the workaround for
* errata 1262606 and 1275112 but applies to a wider
* revision range.
* Inputs:
* x0: variant[4:7] and revision[0:3] of current cpu.
* Shall clobber: x0-x17
* --------------------------------------------------
*/
func errata_n1_1868343_wa
/*
* Compare x0 against revision r4p0
*/
mov x17, x30
bl check_errata_1868343
cbz x0, 1f
mrs x1, NEOVERSE_N1_CPUACTLR_EL1
orr x1, x1, NEOVERSE_N1_CPUACTLR_EL1_BIT_13
msr NEOVERSE_N1_CPUACTLR_EL1, x1
isb
1:
ret x17
endfunc errata_n1_1868343_wa
func check_errata_1868343
/* Applies to everything <= r4p0 */
mov x1, #0x40
b cpu_rev_var_ls
endfunc check_errata_1868343
Workaround for Cortex N1 erratum 1946160 Cortex N1 erratum 1946160 is a Cat B erratum present in r0p0, r1p0, r2p0, r3p0, r3p1, r4p0, and r4p1. The workaround is to insert a DMB ST before acquire atomic instructions without release semantics. This issue is present starting from r0p0 but this workaround applies to revisions r3p0, r3p1, r4p0, and r4p1, for previous revisions there is no workaround. SDEN can be found here: https://documentation-service.arm.com/static/5fa9304cd8dacc30eded464f Signed-off-by: John Powell <john.powell@arm.com> Change-Id: I36e4d6728c275f1c2477dcee9b351077cf7c53e4
2020-10-07 20:33:15 +01:00
/* --------------------------------------------------
* Errata Workaround for Neoverse N1 Errata #1946160.
* This applies to revisions r3p0, r3p1, r4p0, and
* r4p1 of Neoverse N1. It also exists in r0p0, r1p0,
* and r2p0 but there is no fix in these revisions.
* Inputs:
* x0: variant[4:7] and revision[0:3] of current cpu.
* Shall clobber: x0-x17
* --------------------------------------------------
*/
func errata_n1_1946160_wa
/*
* Compare x0 against r3p0 - r4p1
*/
mov x17, x30
bl check_errata_1946160
cbz x0, 1f
mov x0, #3
msr S3_6_C15_C8_0, x0
ldr x0, =0x10E3900002
msr S3_6_C15_C8_2, x0
ldr x0, =0x10FFF00083
msr S3_6_C15_C8_3, x0
ldr x0, =0x2001003FF
msr S3_6_C15_C8_1, x0
mov x0, #4
msr S3_6_C15_C8_0, x0
ldr x0, =0x10E3800082
msr S3_6_C15_C8_2, x0
ldr x0, =0x10FFF00083
msr S3_6_C15_C8_3, x0
ldr x0, =0x2001003FF
msr S3_6_C15_C8_1, x0
mov x0, #5
msr S3_6_C15_C8_0, x0
ldr x0, =0x10E3800200
msr S3_6_C15_C8_2, x0
ldr x0, =0x10FFF003E0
msr S3_6_C15_C8_3, x0
ldr x0, =0x2001003FF
msr S3_6_C15_C8_1, x0
isb
1:
ret x17
endfunc errata_n1_1946160_wa
func check_errata_1946160
/* Applies to r3p0 - r4p1. */
mov x1, #0x30
mov x2, #0x41
b cpu_rev_var_range
endfunc check_errata_1946160
fix(security): workaround for CVE-2022-23960 Implements the loop workaround for Cortex-A77, Cortex-A78, Cortex-A710, Cortex-X2, Neoverse N1, Neoverse N2 and Neoverse V1 CPUs. Signed-off-by: Bipin Ravi <bipin.ravi@arm.com> Change-Id: I11d342df7a2068a15e18f4974c645af3b341235b
2022-01-18 07:59:06 +00:00
func check_errata_cve_2022_23960
#if WORKAROUND_CVE_2022_23960
mov x0, #ERRATA_APPLIES
#else
mov x0, #ERRATA_MISSING
#endif
ret
endfunc check_errata_cve_2022_23960
Rename Cortex-Ares to Neoverse N1 Change-Id: Ideb49011da35f39ff1959be6f5015fa212ca2b6b Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
2019-02-19 13:49:06 +00:00
func neoverse_n1_reset_func
Implement Cortex-Ares 1043202 erratum workaround The workaround uses the instruction patching feature of the Ares cpu. Change-Id: I868fce0dc0e8e41853dcce311f01ee3867aabb59 Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
2018-03-26 16:46:01 +01:00
mov x19, x30
Apply variant 4 mitigation for Neoverse N1 This patch applies the new MSR instruction to directly set the PSTATE.SSBS bit which controls speculative loads. This new instruction is available at Neoverse N1 core so it's utilised. Change-Id: Iee18a8b042c90fdb72d2b98f364dcfbb17510728 Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
2019-03-04 16:41:26 +00:00
Disable speculative loads only if SSBS is supported Examine the ID_AA64PFR1_EL1 bits 7:4 to see if speculative loads (SSBS) is implemented, before disabling speculative loads. Change-Id: I7607c45ed2889260d22a94f6fd9af804520acf67 Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
2019-05-10 14:28:37 +01:00
bl neoverse_n1_disable_speculative_loads
Apply variant 4 mitigation for Neoverse N1 This patch applies the new MSR instruction to directly set the PSTATE.SSBS bit which controls speculative loads. This new instruction is available at Neoverse N1 core so it's utilised. Change-Id: Iee18a8b042c90fdb72d2b98f364dcfbb17510728 Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
2019-03-04 16:41:26 +00:00
Neoverse N1: Forces cacheable atomic to near This patch forces all cacheable atomic instructions to be near, which improves performance in highly contended parallelized use-cases. Change-Id: I93fac62847f4af8d5eaaf3b52318c30893e947d3 Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
2019-04-18 14:34:11 +01:00
/* Forces all cacheable atomic instructions to be near */
mrs x0, NEOVERSE_N1_CPUACTLR2_EL1
orr x0, x0, #NEOVERSE_N1_CPUACTLR2_EL1_BIT_2
msr NEOVERSE_N1_CPUACTLR2_EL1, x0
isb
Implement Cortex-Ares 1043202 erratum workaround The workaround uses the instruction patching feature of the Ares cpu. Change-Id: I868fce0dc0e8e41853dcce311f01ee3867aabb59 Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
2018-03-26 16:46:01 +01:00
bl cpu_get_rev_var
mov x18, x0
Rename Cortex-Ares to Neoverse N1 Change-Id: Ideb49011da35f39ff1959be6f5015fa212ca2b6b Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
2019-02-19 13:49:06 +00:00
#if ERRATA_N1_1043202
Implement Cortex-Ares 1043202 erratum workaround The workaround uses the instruction patching feature of the Ares cpu. Change-Id: I868fce0dc0e8e41853dcce311f01ee3867aabb59 Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
2018-03-26 16:46:01 +01:00
mov x0, x18
Rename Cortex-Ares to Neoverse N1 Change-Id: Ideb49011da35f39ff1959be6f5015fa212ca2b6b Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
2019-02-19 13:49:06 +00:00
bl errata_n1_1043202_wa
Implement Cortex-Ares 1043202 erratum workaround The workaround uses the instruction patching feature of the Ares cpu. Change-Id: I868fce0dc0e8e41853dcce311f01ee3867aabb59 Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
2018-03-26 16:46:01 +01:00
#endif
Workaround for Neoverse N1 erratum 1073348 Neoverse N1 erratum 1073348 is a Cat B erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set a bit in the implementation defined CPUACTLR_EL1 system register, which disables static prediction. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Change-Id: I674126c0af6e068eecb379a190bcf7c75dcbca8e Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
2019-06-24 17:23:50 +01:00
#if ERRATA_N1_1073348
mov x0, x18
bl errata_n1_1073348_wa
#endif
Workaround for Neoverse N1 erratum 1130799 Neoverse N1 erratum 1130799 is a Cat B erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set a bit in the implementation defined CPUACTLR2_EL1 system register. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Change-Id: I252bc45f9733443ba0503fefe62f50fdea61da6d Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
2019-06-24 17:28:34 +01:00
#if ERRATA_N1_1130799
mov x0, x18
bl errata_n1_1130799_wa
#endif
Workaround for Neoverse N1 erratum 1165347 Neoverse N1 erratum 1165347 is a Cat B erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set two bits in the implementation defined CPUACTLR2_EL1 system register. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Change-Id: I163d0ea00578245c1323d2340314cdc3088c450d Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
2019-06-24 17:32:40 +01:00
#if ERRATA_N1_1165347
mov x0, x18
bl errata_n1_1165347_wa
#endif
Workaround for Neoverse N1 erratum 1207823 Neoverse N1 erratum 1207823 is a Cat B erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set a bit in the implementation defined CPUACTLR2_EL1 system register. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Change-Id: Ia932337821f1ef0d644db3612480462a8d924d21 Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
2019-06-24 17:35:37 +01:00
#if ERRATA_N1_1207823
mov x0, x18
bl errata_n1_1207823_wa
#endif
Workaround for Neoverse N1 erratum 1220197 Neoverse N1 erratum 1220197 is a Cat B erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set two bits in the implementation defined CPUECTLR_EL1 system register, which disables write streaming to the L2. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Change-Id: I9c3373f1b6d67d21ee71b2b80aec5e96826818e8 Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
2019-06-24 17:38:53 +01:00
#if ERRATA_N1_1220197
mov x0, x18
bl errata_n1_1220197_wa
#endif
Workaround for Neoverse N1 erratum 1257314 Neoverse N1 erratum 1257314 is a Cat B erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set a bit in the implementation defined CPUACTLR3_EL1 system register, which prevents parallel execution of divide and square root instructions. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Change-Id: I54f0f40ff9043efee40d51e796b92ed85b394cbb Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
2019-06-24 17:42:02 +01:00
#if ERRATA_N1_1257314
mov x0, x18
bl errata_n1_1257314_wa
#endif
Workaround for Neoverse N1 erratum 1262606 Neoverse N1 erratum 1262606 is a Cat B erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set a bit in the implementation defined CPUACTLR_EL1 system register, which delays instruction fetch after branch misprediction. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Change-Id: Idd980e9d5310232d38f0ce272862e1fb0f02ce9a Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
2019-06-24 17:44:58 +01:00
#if ERRATA_N1_1262606
mov x0, x18
bl errata_n1_1262606_wa
#endif
Workaround for Neoverse N1 erratum 1262888 Neoverse N1 erratum 1262888 is a Cat B erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set a bit in the implementation defined CPUECTLR_EL1 system register, which disables the MMU hardware prefetcher. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Change-Id: Ib733d748e32a7ea6a2783f3d5a9c5e13eee01105 Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
2019-06-24 17:47:30 +01:00
#if ERRATA_N1_1262888
mov x0, x18
bl errata_n1_1262888_wa
#endif
Workaround for Neoverse N1 erratum 1275112 Neoverse N1 erratum 1275112 is a Cat B erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set a bit in the implementation defined CPUACTLR_EL1 system register, which delays instruction fetch after branch misprediction. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Change-Id: If7fe55fe92e656fa6aea12327ab297f2e6119833 Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
2019-06-24 17:49:01 +01:00
#if ERRATA_N1_1275112
mov x0, x18
bl errata_n1_1275112_wa
#endif
Neoverse N1: Introduce workaround for Neoverse N1 erratum 1315703 Neoverse N1 erratum 1315703 is a Cat A (rare) erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set a bit in the implementation defined CPUACTLR2_EL1 system register, which will disable the load-bypass-store feature. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdocpjdoc-466751330-1032/index.html Change-Id: I5c708dbe0efa4daa0bcb6bd9622c5efe19c03af9 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2019-05-20 14:57:06 +01:00
#if ERRATA_N1_1315703
mov x0, x18
bl errata_n1_1315703_wa
#endif
Neoverse N1 Errata Workaround 1542419 Coherent I-cache is causing a prefetch violation where when the core executes an instruction that has recently been modified, the core might fetch a stale instruction which violates the ordering of instruction fetches. The workaround includes an instruction sequence to implementation defined registers to trap all EL0 IC IVAU instructions to EL3 and a trap handler to execute a TLB inner-shareable invalidation to an arbitrary address followed by a DSB. Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com> Change-Id: Ic3b7cbb11cf2eaf9005523ef5578a372593ae4d6
2019-08-20 21:51:24 +01:00
#if ERRATA_N1_1542419
mov x0, x18
bl errata_n1_1542419_wa
#endif
Workaround for Neoverse N1 erratum 1868343 Neoverse N1 erratum 1868343 is a Cat B erratum, present in older revisions of the Neoverse N1 processor core. The workaround is to set a bit in the CPUACTLR_EL1 system register, which delays instruction fetch after branch misprediction. This workaround will have a small impact on performance. SDEN can be found here: https://documentation-service.arm.com/static/5f2c130260a93e65927bc92f Signed-off-by: John Powell <john.powell@arm.com> Change-Id: I37da2b3b2da697701b883bff9a1eff2772352844
2020-08-05 18:27:12 +01:00
#if ERRATA_N1_1868343
mov x0, x18
bl errata_n1_1868343_wa
#endif
Workaround for Cortex N1 erratum 1946160 Cortex N1 erratum 1946160 is a Cat B erratum present in r0p0, r1p0, r2p0, r3p0, r3p1, r4p0, and r4p1. The workaround is to insert a DMB ST before acquire atomic instructions without release semantics. This issue is present starting from r0p0 but this workaround applies to revisions r3p0, r3p1, r4p0, and r4p1, for previous revisions there is no workaround. SDEN can be found here: https://documentation-service.arm.com/static/5fa9304cd8dacc30eded464f Signed-off-by: John Powell <john.powell@arm.com> Change-Id: I36e4d6728c275f1c2477dcee9b351077cf7c53e4
2020-10-07 20:33:15 +01:00
#if ERRATA_N1_1946160
mov x0, x18
bl errata_n1_1946160_wa
#endif
Add AMU support for Cortex-Ares Change-Id: Ia170c12d3929a616ba80eb7645c301066641f5cc Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
2018-02-13 11:28:02 +00:00
#if ENABLE_AMU
/* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */
mrs x0, actlr_el3
Rename Cortex-Ares to Neoverse N1 Change-Id: Ideb49011da35f39ff1959be6f5015fa212ca2b6b Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
2019-02-19 13:49:06 +00:00
orr x0, x0, #NEOVERSE_N1_ACTLR_AMEN_BIT
Add AMU support for Cortex-Ares Change-Id: Ia170c12d3929a616ba80eb7645c301066641f5cc Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
2018-02-13 11:28:02 +00:00
msr actlr_el3, x0
/* Make sure accesses from EL0/EL1 are not trapped to EL2 */
mrs x0, actlr_el2
Rename Cortex-Ares to Neoverse N1 Change-Id: Ideb49011da35f39ff1959be6f5015fa212ca2b6b Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
2019-02-19 13:49:06 +00:00
orr x0, x0, #NEOVERSE_N1_ACTLR_AMEN_BIT
Add AMU support for Cortex-Ares Change-Id: Ia170c12d3929a616ba80eb7645c301066641f5cc Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
2018-02-13 11:28:02 +00:00
msr actlr_el2, x0
/* Enable group0 counters */
Rename Cortex-Ares to Neoverse N1 Change-Id: Ideb49011da35f39ff1959be6f5015fa212ca2b6b Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
2019-02-19 13:49:06 +00:00
mov x0, #NEOVERSE_N1_AMU_GROUP0_MASK
Add AMU support for Cortex-Ares Change-Id: Ia170c12d3929a616ba80eb7645c301066641f5cc Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
2018-02-13 11:28:02 +00:00
msr CPUAMCNTENSET_EL0, x0
#endif
DSU: Apply erratum 936184 for Neoverse N1/E1 Change-Id: Idd08914bcb945ad6aa0621e594c95df88ee8f9c8 Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
2019-06-10 16:43:39 +01:00
Add support for Neoverse-N2 CPUs. Enable basic support for Neoverse-N2 CPUs. Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com> Change-Id: I498adc2d9fc61ac6e1af8ece131039410872e8ad
2020-10-23 13:22:07 +01:00
#if NEOVERSE_Nx_EXTERNAL_LLC
Neovers N1: added support to update presence of External LLC CPUECTLR_EL1.EXTLLC bit indicates the presense of internal or external last level cache(LLC) in the system, the reset value is internal LLC. To cater for the platforms(like N1SDP) which has external LLC present introduce a new build option 'NEOVERSE_N1_EXTERNAL_LLC' which can be enabled by platform port. Signed-off-by: Manish Pandey <manish.pandey2@arm.com> Change-Id: Ibf475fcd6fd44401897a71600f4eafe989921363
2020-01-24 11:54:44 +00:00
/* Some system may have External LLC, core needs to be made aware */
mrs x0, NEOVERSE_N1_CPUECTLR_EL1
orr x0, x0, NEOVERSE_N1_CPUECTLR_EL1_EXTLLC_BIT
msr NEOVERSE_N1_CPUECTLR_EL1, x0
#endif
DSU: Apply erratum 936184 for Neoverse N1/E1 Change-Id: Idd08914bcb945ad6aa0621e594c95df88ee8f9c8 Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
2019-06-10 16:43:39 +01:00
#if ERRATA_DSU_936184
bl errata_dsu_936184_wa
#endif
fix(security): workaround for CVE-2022-23960 Implements the loop workaround for Cortex-A77, Cortex-A78, Cortex-A710, Cortex-X2, Neoverse N1, Neoverse N2 and Neoverse V1 CPUs. Signed-off-by: Bipin Ravi <bipin.ravi@arm.com> Change-Id: I11d342df7a2068a15e18f4974c645af3b341235b
2022-01-18 07:59:06 +00:00
#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960
/*
* The Neoverse-N1 generic vectors are overridden to apply errata
* mitigation on exception entry from lower ELs.
*/
adr x0, wa_cve_vbar_neoverse_n1
msr vbar_el3, x0
#endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */
Removing redundant ISB instructions Replacing ISB instructions in each Errata workaround with a single ISB instruction before the RET in the reset handler. Change-Id: I08afabc5b98986a6fe81664cd13822b36cab786f Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
2019-06-27 17:03:25 +01:00
isb
Implement Cortex-Ares 1043202 erratum workaround The workaround uses the instruction patching feature of the Ares cpu. Change-Id: I868fce0dc0e8e41853dcce311f01ee3867aabb59 Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
2018-03-26 16:46:01 +01:00
ret x19
Rename Cortex-Ares to Neoverse N1 Change-Id: Ideb49011da35f39ff1959be6f5015fa212ca2b6b Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
2019-02-19 13:49:06 +00:00
endfunc neoverse_n1_reset_func
Add support for Cortex-Ares and Cortex-A76 CPUs Both Cortex-Ares and Cortex-A76 CPUs use the ARM DynamIQ Shared Unit (DSU). The power-down and power-up sequences are therefore mostly managed in hardware, and required software operations are simple. Change-Id: I3a9447b5bdbdbc5ed845b20f6564d086516fa161 Signed-off-by: Isla Mitchell <isla.mitchell@arm.com>
2017-08-03 16:04:46 +01:00
/* ---------------------------------------------
* HW will do the cache maintenance while powering down
* ---------------------------------------------
*/
Rename Cortex-Ares to Neoverse N1 Change-Id: Ideb49011da35f39ff1959be6f5015fa212ca2b6b Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
2019-02-19 13:49:06 +00:00
func neoverse_n1_core_pwr_dwn
Add support for Cortex-Ares and Cortex-A76 CPUs Both Cortex-Ares and Cortex-A76 CPUs use the ARM DynamIQ Shared Unit (DSU). The power-down and power-up sequences are therefore mostly managed in hardware, and required software operations are simple. Change-Id: I3a9447b5bdbdbc5ed845b20f6564d086516fa161 Signed-off-by: Isla Mitchell <isla.mitchell@arm.com>
2017-08-03 16:04:46 +01:00
/* ---------------------------------------------
* Enable CPU power down bit in power control register
* ---------------------------------------------
*/
Rename Cortex-Ares to Neoverse N1 Change-Id: Ideb49011da35f39ff1959be6f5015fa212ca2b6b Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
2019-02-19 13:49:06 +00:00
mrs x0, NEOVERSE_N1_CPUPWRCTLR_EL1
orr x0, x0, #NEOVERSE_N1_CORE_PWRDN_EN_MASK
msr NEOVERSE_N1_CPUPWRCTLR_EL1, x0
Add support for Cortex-Ares and Cortex-A76 CPUs Both Cortex-Ares and Cortex-A76 CPUs use the ARM DynamIQ Shared Unit (DSU). The power-down and power-up sequences are therefore mostly managed in hardware, and required software operations are simple. Change-Id: I3a9447b5bdbdbc5ed845b20f6564d086516fa161 Signed-off-by: Isla Mitchell <isla.mitchell@arm.com>
2017-08-03 16:04:46 +01:00
isb
ret
Rename Cortex-Ares to Neoverse N1 Change-Id: Ideb49011da35f39ff1959be6f5015fa212ca2b6b Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
2019-02-19 13:49:06 +00:00
endfunc neoverse_n1_core_pwr_dwn
Add support for Cortex-Ares and Cortex-A76 CPUs Both Cortex-Ares and Cortex-A76 CPUs use the ARM DynamIQ Shared Unit (DSU). The power-down and power-up sequences are therefore mostly managed in hardware, and required software operations are simple. Change-Id: I3a9447b5bdbdbc5ed845b20f6564d086516fa161 Signed-off-by: Isla Mitchell <isla.mitchell@arm.com>
2017-08-03 16:04:46 +01:00
Implement Cortex-Ares 1043202 erratum workaround The workaround uses the instruction patching feature of the Ares cpu. Change-Id: I868fce0dc0e8e41853dcce311f01ee3867aabb59 Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
2018-03-26 16:46:01 +01:00
#if REPORT_ERRATA
/*
Rename Cortex-Ares to Neoverse N1 Change-Id: Ideb49011da35f39ff1959be6f5015fa212ca2b6b Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
2019-02-19 13:49:06 +00:00
* Errata printing function for Neoverse N1. Must follow AAPCS.
Implement Cortex-Ares 1043202 erratum workaround The workaround uses the instruction patching feature of the Ares cpu. Change-Id: I868fce0dc0e8e41853dcce311f01ee3867aabb59 Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
2018-03-26 16:46:01 +01:00
*/
Rename Cortex-Ares to Neoverse N1 Change-Id: Ideb49011da35f39ff1959be6f5015fa212ca2b6b Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
2019-02-19 13:49:06 +00:00
func neoverse_n1_errata_report
Implement Cortex-Ares 1043202 erratum workaround The workaround uses the instruction patching feature of the Ares cpu. Change-Id: I868fce0dc0e8e41853dcce311f01ee3867aabb59 Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
2018-03-26 16:46:01 +01:00
stp x8, x30, [sp, #-16]!
bl cpu_get_rev_var
mov x8, x0
/*
* Report all errata. The revision-variant information is passed to
* checking functions of each errata.
*/
Rename Cortex-Ares to Neoverse N1 Change-Id: Ideb49011da35f39ff1959be6f5015fa212ca2b6b Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
2019-02-19 13:49:06 +00:00
report_errata ERRATA_N1_1043202, neoverse_n1, 1043202
Workaround for Neoverse N1 erratum 1073348 Neoverse N1 erratum 1073348 is a Cat B erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set a bit in the implementation defined CPUACTLR_EL1 system register, which disables static prediction. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Change-Id: I674126c0af6e068eecb379a190bcf7c75dcbca8e Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
2019-06-24 17:23:50 +01:00
report_errata ERRATA_N1_1073348, neoverse_n1, 1073348
Workaround for Neoverse N1 erratum 1130799 Neoverse N1 erratum 1130799 is a Cat B erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set a bit in the implementation defined CPUACTLR2_EL1 system register. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Change-Id: I252bc45f9733443ba0503fefe62f50fdea61da6d Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
2019-06-24 17:28:34 +01:00
report_errata ERRATA_N1_1130799, neoverse_n1, 1130799
Workaround for Neoverse N1 erratum 1165347 Neoverse N1 erratum 1165347 is a Cat B erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set two bits in the implementation defined CPUACTLR2_EL1 system register. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Change-Id: I163d0ea00578245c1323d2340314cdc3088c450d Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
2019-06-24 17:32:40 +01:00
report_errata ERRATA_N1_1165347, neoverse_n1, 1165347
Workaround for Neoverse N1 erratum 1207823 Neoverse N1 erratum 1207823 is a Cat B erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set a bit in the implementation defined CPUACTLR2_EL1 system register. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Change-Id: Ia932337821f1ef0d644db3612480462a8d924d21 Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
2019-06-24 17:35:37 +01:00
report_errata ERRATA_N1_1207823, neoverse_n1, 1207823
Workaround for Neoverse N1 erratum 1220197 Neoverse N1 erratum 1220197 is a Cat B erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set two bits in the implementation defined CPUECTLR_EL1 system register, which disables write streaming to the L2. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Change-Id: I9c3373f1b6d67d21ee71b2b80aec5e96826818e8 Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
2019-06-24 17:38:53 +01:00
report_errata ERRATA_N1_1220197, neoverse_n1, 1220197
Workaround for Neoverse N1 erratum 1257314 Neoverse N1 erratum 1257314 is a Cat B erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set a bit in the implementation defined CPUACTLR3_EL1 system register, which prevents parallel execution of divide and square root instructions. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Change-Id: I54f0f40ff9043efee40d51e796b92ed85b394cbb Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
2019-06-24 17:42:02 +01:00
report_errata ERRATA_N1_1257314, neoverse_n1, 1257314
Workaround for Neoverse N1 erratum 1262606 Neoverse N1 erratum 1262606 is a Cat B erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set a bit in the implementation defined CPUACTLR_EL1 system register, which delays instruction fetch after branch misprediction. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Change-Id: Idd980e9d5310232d38f0ce272862e1fb0f02ce9a Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
2019-06-24 17:44:58 +01:00
report_errata ERRATA_N1_1262606, neoverse_n1, 1262606
Workaround for Neoverse N1 erratum 1262888 Neoverse N1 erratum 1262888 is a Cat B erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set a bit in the implementation defined CPUECTLR_EL1 system register, which disables the MMU hardware prefetcher. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Change-Id: Ib733d748e32a7ea6a2783f3d5a9c5e13eee01105 Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
2019-06-24 17:47:30 +01:00
report_errata ERRATA_N1_1262888, neoverse_n1, 1262888
Workaround for Neoverse N1 erratum 1275112 Neoverse N1 erratum 1275112 is a Cat B erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set a bit in the implementation defined CPUACTLR_EL1 system register, which delays instruction fetch after branch misprediction. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Change-Id: If7fe55fe92e656fa6aea12327ab297f2e6119833 Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
2019-06-24 17:49:01 +01:00
report_errata ERRATA_N1_1275112, neoverse_n1, 1275112
Neoverse N1: Introduce workaround for Neoverse N1 erratum 1315703 Neoverse N1 erratum 1315703 is a Cat A (rare) erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set a bit in the implementation defined CPUACTLR2_EL1 system register, which will disable the load-bypass-store feature. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdocpjdoc-466751330-1032/index.html Change-Id: I5c708dbe0efa4daa0bcb6bd9622c5efe19c03af9 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2019-05-20 14:57:06 +01:00
report_errata ERRATA_N1_1315703, neoverse_n1, 1315703
Neoverse N1 Errata Workaround 1542419 Coherent I-cache is causing a prefetch violation where when the core executes an instruction that has recently been modified, the core might fetch a stale instruction which violates the ordering of instruction fetches. The workaround includes an instruction sequence to implementation defined registers to trap all EL0 IC IVAU instructions to EL3 and a trap handler to execute a TLB inner-shareable invalidation to an arbitrary address followed by a DSB. Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com> Change-Id: Ic3b7cbb11cf2eaf9005523ef5578a372593ae4d6
2019-08-20 21:51:24 +01:00
report_errata ERRATA_N1_1542419, neoverse_n1, 1542419
Workaround for Neoverse N1 erratum 1868343 Neoverse N1 erratum 1868343 is a Cat B erratum, present in older revisions of the Neoverse N1 processor core. The workaround is to set a bit in the CPUACTLR_EL1 system register, which delays instruction fetch after branch misprediction. This workaround will have a small impact on performance. SDEN can be found here: https://documentation-service.arm.com/static/5f2c130260a93e65927bc92f Signed-off-by: John Powell <john.powell@arm.com> Change-Id: I37da2b3b2da697701b883bff9a1eff2772352844
2020-08-05 18:27:12 +01:00
report_errata ERRATA_N1_1868343, neoverse_n1, 1868343
Workaround for Cortex N1 erratum 1946160 Cortex N1 erratum 1946160 is a Cat B erratum present in r0p0, r1p0, r2p0, r3p0, r3p1, r4p0, and r4p1. The workaround is to insert a DMB ST before acquire atomic instructions without release semantics. This issue is present starting from r0p0 but this workaround applies to revisions r3p0, r3p1, r4p0, and r4p1, for previous revisions there is no workaround. SDEN can be found here: https://documentation-service.arm.com/static/5fa9304cd8dacc30eded464f Signed-off-by: John Powell <john.powell@arm.com> Change-Id: I36e4d6728c275f1c2477dcee9b351077cf7c53e4
2020-10-07 20:33:15 +01:00
report_errata ERRATA_N1_1946160, neoverse_n1, 1946160
DSU: Apply erratum 936184 for Neoverse N1/E1 Change-Id: Idd08914bcb945ad6aa0621e594c95df88ee8f9c8 Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
2019-06-10 16:43:39 +01:00
report_errata ERRATA_DSU_936184, neoverse_n1, dsu_936184
fix(security): workaround for CVE-2022-23960 Implements the loop workaround for Cortex-A77, Cortex-A78, Cortex-A710, Cortex-X2, Neoverse N1, Neoverse N2 and Neoverse V1 CPUs. Signed-off-by: Bipin Ravi <bipin.ravi@arm.com> Change-Id: I11d342df7a2068a15e18f4974c645af3b341235b
2022-01-18 07:59:06 +00:00
report_errata WORKAROUND_CVE_2022_23960, neoverse_n1, cve_2022_23960
Implement Cortex-Ares 1043202 erratum workaround The workaround uses the instruction patching feature of the Ares cpu. Change-Id: I868fce0dc0e8e41853dcce311f01ee3867aabb59 Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
2018-03-26 16:46:01 +01:00
ldp x8, x30, [sp], #16
ret
Rename Cortex-Ares to Neoverse N1 Change-Id: Ideb49011da35f39ff1959be6f5015fa212ca2b6b Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
2019-02-19 13:49:06 +00:00
endfunc neoverse_n1_errata_report
Implement Cortex-Ares 1043202 erratum workaround The workaround uses the instruction patching feature of the Ares cpu. Change-Id: I868fce0dc0e8e41853dcce311f01ee3867aabb59 Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
2018-03-26 16:46:01 +01:00
#endif
Neoverse N1 Errata Workaround 1542419 Coherent I-cache is causing a prefetch violation where when the core executes an instruction that has recently been modified, the core might fetch a stale instruction which violates the ordering of instruction fetches. The workaround includes an instruction sequence to implementation defined registers to trap all EL0 IC IVAU instructions to EL3 and a trap handler to execute a TLB inner-shareable invalidation to an arbitrary address followed by a DSB. Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com> Change-Id: Ic3b7cbb11cf2eaf9005523ef5578a372593ae4d6
2019-08-20 21:51:24 +01:00
/*
* Handle trap of EL0 IC IVAU instructions to EL3 by executing a TLB
* inner-shareable invalidation to an arbitrary address followed by a DSB.
*
* x1: Exception Syndrome
*/
func neoverse_n1_errata_ic_trap_handler
cmp x1, #NEOVERSE_N1_EC_IC_TRAP
b.ne 1f
tlbi vae3is, xzr
dsb sy
Fix white space errors + remove #if defined Fix a few white space errors and remove #if defined in workaround for N1 Errata 1542419. Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com> Change-Id: I07ac5a2fd50cd63de53c06e3d0f8262871b62fad
2019-10-11 21:45:24 +01:00
# Skip the IC instruction itself
mrs x3, elr_el3
add x3, x3, #4
msr elr_el3, x3
Neoverse N1 Errata Workaround 1542419 Coherent I-cache is causing a prefetch violation where when the core executes an instruction that has recently been modified, the core might fetch a stale instruction which violates the ordering of instruction fetches. The workaround includes an instruction sequence to implementation defined registers to trap all EL0 IC IVAU instructions to EL3 and a trap handler to execute a TLB inner-shareable invalidation to an arbitrary address followed by a DSB. Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com> Change-Id: Ic3b7cbb11cf2eaf9005523ef5578a372593ae4d6
2019-08-20 21:51:24 +01:00
ldp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0]
ldp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2]
ldp x4, x5, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X4]
ldr x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
#if IMAGE_BL31 && RAS_EXTENSION
/*
* Issue Error Synchronization Barrier to synchronize SErrors before
* exiting EL3. We're running with EAs unmasked, so any synchronized
* errors would be taken immediately; therefore no need to inspect
* DISR_EL1 register.
*/
esb
#endif
Prevent speculative execution past ERET Even though ERET always causes a jump to another address, aarch64 CPUs speculatively execute following instructions as if the ERET instruction was not a jump instruction. The speculative execution does not cross privilege-levels (to the jump target as one would expect), but it continues on the kernel privilege level as if the ERET instruction did not change the control flow - thus execution anything that is accidentally linked after the ERET instruction. Later, the results of this speculative execution are always architecturally discarded, however they can leak data using microarchitectural side channels. This speculative execution is very reliable (seems to be unconditional) and it manages to complete even relatively performance-heavy operations (e.g. multiple dependent fetches from uncached memory). This was fixed in Linux, FreeBSD, OpenBSD and Optee OS: https://github.com/torvalds/linux/commit/679db70801da9fda91d26caf13bf5b5ccc74e8e8 https://github.com/freebsd/freebsd/commit/29fb48ace4186a41c409fde52bcf4216e9e50b61 https://github.com/openbsd/src/commit/3a08873ece1cb28ace89fd65e8f3c1375cc98de2 https://github.com/OP-TEE/optee_os/commit/abfd092aa19f9c0251e3d5551e2d68a9ebcfec8a It is demonstrated in a SafeSide example: https://github.com/google/safeside/blob/master/demos/eret_hvc_smc_wrapper.cc https://github.com/google/safeside/blob/master/kernel_modules/kmod_eret_hvc_smc/eret_hvc_smc_module.c Signed-off-by: Anthony Steinhauser <asteinhauser@google.com> Change-Id: Iead39b0b9fb4b8d8b5609daaa8be81497ba63a0f
2020-01-07 23:44:06 +00:00
exception_return
Neoverse N1 Errata Workaround 1542419 Coherent I-cache is causing a prefetch violation where when the core executes an instruction that has recently been modified, the core might fetch a stale instruction which violates the ordering of instruction fetches. The workaround includes an instruction sequence to implementation defined registers to trap all EL0 IC IVAU instructions to EL3 and a trap handler to execute a TLB inner-shareable invalidation to an arbitrary address followed by a DSB. Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com> Change-Id: Ic3b7cbb11cf2eaf9005523ef5578a372593ae4d6
2019-08-20 21:51:24 +01:00
1:
ret
endfunc neoverse_n1_errata_ic_trap_handler
Add support for Cortex-Ares and Cortex-A76 CPUs Both Cortex-Ares and Cortex-A76 CPUs use the ARM DynamIQ Shared Unit (DSU). The power-down and power-up sequences are therefore mostly managed in hardware, and required software operations are simple. Change-Id: I3a9447b5bdbdbc5ed845b20f6564d086516fa161 Signed-off-by: Isla Mitchell <isla.mitchell@arm.com>
2017-08-03 16:04:46 +01:00
/* ---------------------------------------------
Rename Cortex-Ares to Neoverse N1 Change-Id: Ideb49011da35f39ff1959be6f5015fa212ca2b6b Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
2019-02-19 13:49:06 +00:00
* This function provides neoverse_n1 specific
Add support for Cortex-Ares and Cortex-A76 CPUs Both Cortex-Ares and Cortex-A76 CPUs use the ARM DynamIQ Shared Unit (DSU). The power-down and power-up sequences are therefore mostly managed in hardware, and required software operations are simple. Change-Id: I3a9447b5bdbdbc5ed845b20f6564d086516fa161 Signed-off-by: Isla Mitchell <isla.mitchell@arm.com>
2017-08-03 16:04:46 +01:00
* register information for crash reporting.
* It needs to return with x6 pointing to
* a list of register names in ascii and
* x8 - x15 having values of registers to be
* reported.
* ---------------------------------------------
*/
Rename Cortex-Ares to Neoverse N1 Change-Id: Ideb49011da35f39ff1959be6f5015fa212ca2b6b Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
2019-02-19 13:49:06 +00:00
.section .rodata.neoverse_n1_regs, "aS"
neoverse_n1_regs: /* The ascii list of register names to be reported */
Add support for Cortex-Ares and Cortex-A76 CPUs Both Cortex-Ares and Cortex-A76 CPUs use the ARM DynamIQ Shared Unit (DSU). The power-down and power-up sequences are therefore mostly managed in hardware, and required software operations are simple. Change-Id: I3a9447b5bdbdbc5ed845b20f6564d086516fa161 Signed-off-by: Isla Mitchell <isla.mitchell@arm.com>
2017-08-03 16:04:46 +01:00
.asciz "cpuectlr_el1", ""
Rename Cortex-Ares to Neoverse N1 Change-Id: Ideb49011da35f39ff1959be6f5015fa212ca2b6b Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
2019-02-19 13:49:06 +00:00
func neoverse_n1_cpu_reg_dump
adr x6, neoverse_n1_regs
mrs x8, NEOVERSE_N1_CPUECTLR_EL1
Add support for Cortex-Ares and Cortex-A76 CPUs Both Cortex-Ares and Cortex-A76 CPUs use the ARM DynamIQ Shared Unit (DSU). The power-down and power-up sequences are therefore mostly managed in hardware, and required software operations are simple. Change-Id: I3a9447b5bdbdbc5ed845b20f6564d086516fa161 Signed-off-by: Isla Mitchell <isla.mitchell@arm.com>
2017-08-03 16:04:46 +01:00
ret
Rename Cortex-Ares to Neoverse N1 Change-Id: Ideb49011da35f39ff1959be6f5015fa212ca2b6b Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
2019-02-19 13:49:06 +00:00
endfunc neoverse_n1_cpu_reg_dump
Add support for Cortex-Ares and Cortex-A76 CPUs Both Cortex-Ares and Cortex-A76 CPUs use the ARM DynamIQ Shared Unit (DSU). The power-down and power-up sequences are therefore mostly managed in hardware, and required software operations are simple. Change-Id: I3a9447b5bdbdbc5ed845b20f6564d086516fa161 Signed-off-by: Isla Mitchell <isla.mitchell@arm.com>
2017-08-03 16:04:46 +01:00
Neoverse N1 Errata Workaround 1542419 Coherent I-cache is causing a prefetch violation where when the core executes an instruction that has recently been modified, the core might fetch a stale instruction which violates the ordering of instruction fetches. The workaround includes an instruction sequence to implementation defined registers to trap all EL0 IC IVAU instructions to EL3 and a trap handler to execute a TLB inner-shareable invalidation to an arbitrary address followed by a DSB. Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com> Change-Id: Ic3b7cbb11cf2eaf9005523ef5578a372593ae4d6
2019-08-20 21:51:24 +01:00
declare_cpu_ops_eh neoverse_n1, NEOVERSE_N1_MIDR, \
Rename Cortex-Ares to Neoverse N1 Change-Id: Ideb49011da35f39ff1959be6f5015fa212ca2b6b Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
2019-02-19 13:49:06 +00:00
neoverse_n1_reset_func, \
Neoverse N1 Errata Workaround 1542419 Coherent I-cache is causing a prefetch violation where when the core executes an instruction that has recently been modified, the core might fetch a stale instruction which violates the ordering of instruction fetches. The workaround includes an instruction sequence to implementation defined registers to trap all EL0 IC IVAU instructions to EL3 and a trap handler to execute a TLB inner-shareable invalidation to an arbitrary address followed by a DSB. Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com> Change-Id: Ic3b7cbb11cf2eaf9005523ef5578a372593ae4d6
2019-08-20 21:51:24 +01:00
neoverse_n1_errata_ic_trap_handler, \
Rename Cortex-Ares to Neoverse N1 Change-Id: Ideb49011da35f39ff1959be6f5015fa212ca2b6b Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
2019-02-19 13:49:06 +00:00
neoverse_n1_core_pwr_dwn