113 lines
3.6 KiB
C
113 lines
3.6 KiB
C
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/*
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* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __SOC_ROCKCHIP_RK3399_DFS_H__
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#define __SOC_ROCKCHIP_RK3399_DFS_H__
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struct rk3399_sdram_default_config {
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unsigned char bl;
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/* 1:auto precharge, 0:never auto precharge */
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unsigned char ap;
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/* dram driver strength */
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unsigned char dramds;
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/* dram ODT, if odt=0, this parameter invalid */
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unsigned char dramodt;
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/* ca ODT, if odt=0, this parameter invalid
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* only used by LPDDR4
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*/
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unsigned char caodt;
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unsigned char burst_ref_cnt;
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/* zqcs period, unit(s) */
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unsigned char zqcsi;
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};
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struct ddr_dts_config_timing {
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unsigned int ddr3_speed_bin;
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unsigned int pd_idle;
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unsigned int sr_idle;
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unsigned int sr_mc_gate_idle;
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unsigned int srpd_lite_idle;
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unsigned int standby_idle;
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unsigned int auto_pd_dis_freq;
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unsigned int ddr3_dll_dis_freq;
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unsigned int phy_dll_dis_freq;
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unsigned int ddr3_odt_dis_freq;
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unsigned int ddr3_drv;
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unsigned int ddr3_odt;
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unsigned int phy_ddr3_ca_drv;
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unsigned int phy_ddr3_dq_drv;
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unsigned int phy_ddr3_odt;
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unsigned int lpddr3_odt_dis_freq;
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unsigned int lpddr3_drv;
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unsigned int lpddr3_odt;
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unsigned int phy_lpddr3_ca_drv;
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unsigned int phy_lpddr3_dq_drv;
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unsigned int phy_lpddr3_odt;
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unsigned int lpddr4_odt_dis_freq;
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unsigned int lpddr4_drv;
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unsigned int lpddr4_dq_odt;
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unsigned int lpddr4_ca_odt;
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unsigned int phy_lpddr4_ca_drv;
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unsigned int phy_lpddr4_ck_cs_drv;
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unsigned int phy_lpddr4_dq_drv;
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unsigned int phy_lpddr4_odt;
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uint32_t available;
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};
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struct drv_odt_lp_config {
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uint32_t ddr3_speed_bin;
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uint32_t pd_idle;
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uint32_t sr_idle;
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uint32_t sr_mc_gate_idle;
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uint32_t srpd_lite_idle;
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uint32_t standby_idle;
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uint32_t ddr3_dll_dis_freq;/* for ddr3 only */
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uint32_t phy_dll_dis_freq;
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uint32_t odt_dis_freq;
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uint32_t dram_side_drv;
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uint32_t dram_side_dq_odt;
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uint32_t dram_side_ca_odt;
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uint32_t phy_side_ca_drv;
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uint32_t phy_side_ck_cs_drv;
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uint32_t phy_side_dq_drv;
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uint32_t phy_side_odt;
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};
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void ddr_dfs_init(void);
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uint32_t ddr_set_rate(uint32_t hz);
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uint32_t ddr_round_rate(uint32_t hz);
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uint32_t ddr_get_rate(void);
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void clr_dcf_irq(void);
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uint32_t dts_timing_receive(uint32_t timing, uint32_t index);
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#endif
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