2017-11-06 14:49:04 +00:00
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/*
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2018-07-14 02:15:51 +01:00
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* Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
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2017-11-06 14:49:04 +00:00
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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2018-11-08 10:20:19 +00:00
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#ifndef RPI3_HW_H
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#define RPI3_HW_H
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2017-11-06 14:49:04 +00:00
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#include <utils_def.h>
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/*
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* Peripherals
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*/
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#define RPI3_IO_BASE ULL(0x3F000000)
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#define RPI3_IO_SIZE ULL(0x01000000)
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2018-07-12 13:38:53 +01:00
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/*
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* ARM <-> VideoCore mailboxes
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*/
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#define RPI3_MBOX_OFFSET ULL(0x0000B880)
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#define RPI3_MBOX_BASE (RPI3_IO_BASE + RPI3_MBOX_OFFSET)
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/* VideoCore -> ARM */
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#define RPI3_MBOX0_READ_OFFSET ULL(0x00000000)
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#define RPI3_MBOX0_PEEK_OFFSET ULL(0x00000010)
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#define RPI3_MBOX0_SENDER_OFFSET ULL(0x00000014)
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#define RPI3_MBOX0_STATUS_OFFSET ULL(0x00000018)
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#define RPI3_MBOX0_CONFIG_OFFSET ULL(0x0000001C)
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/* ARM -> VideoCore */
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#define RPI3_MBOX1_WRITE_OFFSET ULL(0x00000020)
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#define RPI3_MBOX1_PEEK_OFFSET ULL(0x00000030)
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#define RPI3_MBOX1_SENDER_OFFSET ULL(0x00000034)
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#define RPI3_MBOX1_STATUS_OFFSET ULL(0x00000038)
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#define RPI3_MBOX1_CONFIG_OFFSET ULL(0x0000003C)
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/* Mailbox status constants */
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#define RPI3_MBOX_STATUS_FULL_MASK U(0x80000000) /* Set if full */
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#define RPI3_MBOX_STATUS_EMPTY_MASK U(0x40000000) /* Set if empty */
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2017-11-06 14:49:04 +00:00
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/*
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* Power management, reset controller, watchdog.
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*/
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#define RPI3_IO_PM_OFFSET ULL(0x00100000)
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#define RPI3_PM_BASE (RPI3_IO_BASE + RPI3_IO_PM_OFFSET)
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/* Registers on top of RPI3_PM_BASE. */
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#define RPI3_PM_RSTC_OFFSET ULL(0x0000001C)
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2018-07-14 02:15:51 +01:00
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#define RPI3_PM_RSTS_OFFSET ULL(0x00000020)
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2017-11-06 14:49:04 +00:00
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#define RPI3_PM_WDOG_OFFSET ULL(0x00000024)
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/* Watchdog constants */
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2018-07-14 02:15:51 +01:00
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#define RPI3_PM_PASSWORD U(0x5A000000)
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#define RPI3_PM_RSTC_WRCFG_MASK U(0x00000030)
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#define RPI3_PM_RSTC_WRCFG_FULL_RESET U(0x00000020)
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/*
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* The RSTS register is used by the VideoCore firmware when booting the
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* Raspberry Pi to know which partition to boot from. The partition value is
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* formed by bits 0, 2, 4, 6, 8 and 10. Partition 63 is used by said firmware
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* to indicate halt.
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*/
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#define RPI3_PM_RSTS_WRCFG_HALT U(0x00000555)
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2018-07-13 09:27:16 +01:00
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/*
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* Hardware random number generator.
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*/
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#define RPI3_IO_RNG_OFFSET ULL(0x00104000)
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#define RPI3_RNG_BASE (RPI3_IO_BASE + RPI3_IO_RNG_OFFSET)
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#define RPI3_RNG_CTRL_OFFSET ULL(0x00000000)
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#define RPI3_RNG_STATUS_OFFSET ULL(0x00000004)
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#define RPI3_RNG_DATA_OFFSET ULL(0x00000008)
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#define RPI3_RNG_INT_MASK_OFFSET ULL(0x00000010)
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/* Enable/disable RNG */
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#define RPI3_RNG_CTRL_ENABLE U(0x1)
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#define RPI3_RNG_CTRL_DISABLE U(0x0)
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/* Number of currently available words */
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#define RPI3_RNG_STATUS_NUM_WORDS_SHIFT U(24)
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#define RPI3_RNG_STATUS_NUM_WORDS_MASK U(0xFF)
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/* Value to mask interrupts caused by the RNG */
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#define RPI3_RNG_INT_MASK_DISABLE U(0x1)
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2018-07-14 02:15:51 +01:00
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/*
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* Serial port (called 'Mini UART' in the BCM docucmentation).
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*/
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#define RPI3_IO_MINI_UART_OFFSET ULL(0x00215040)
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#define RPI3_MINI_UART_BASE (RPI3_IO_BASE + RPI3_IO_MINI_UART_OFFSET)
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#define RPI3_MINI_UART_CLK_IN_HZ ULL(500000000)
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2017-11-06 14:49:04 +00:00
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/*
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* Local interrupt controller
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*/
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#define RPI3_INTC_BASE_ADDRESS ULL(0x40000000)
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/* Registers on top of RPI3_INTC_BASE_ADDRESS */
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#define RPI3_INTC_CONTROL_OFFSET ULL(0x00000000)
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#define RPI3_INTC_PRESCALER_OFFSET ULL(0x00000008)
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#define RPI3_INTC_MBOX_CONTROL_OFFSET ULL(0x00000050)
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#define RPI3_INTC_MBOX_CONTROL_SLOT3_FIQ ULL(0x00000080)
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#define RPI3_INTC_PENDING_FIQ_OFFSET ULL(0x00000070)
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#define RPI3_INTC_PENDING_FIQ_MBOX3 ULL(0x00000080)
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2018-11-08 10:20:19 +00:00
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#endif /* RPI3_HW_H */
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