arm-trusted-firmware/include/lib/psci/psci_lib.h

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/*
* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef PSCI_LIB_H
#define PSCI_LIB_H
#include <ep_info.h>
#ifndef __ASSEMBLY__
#include <cdefs.h>
#include <stdint.h>
/*******************************************************************************
* Optional structure populated by the Secure Payload Dispatcher to be given a
* chance to perform any bookkeeping before PSCI executes a power management
* operation. It also allows PSCI to determine certain properties of the SP e.g.
* migrate capability etc.
******************************************************************************/
typedef struct spd_pm_ops {
void (*svc_on)(u_register_t target_cpu);
int32_t (*svc_off)(u_register_t __unused unused);
void (*svc_suspend)(u_register_t max_off_pwrlvl);
void (*svc_on_finish)(u_register_t __unused unused);
void (*svc_suspend_finish)(u_register_t max_off_pwrlvl);
int32_t (*svc_migrate)(u_register_t from_cpu, u_register_t to_cpu);
int32_t (*svc_migrate_info)(u_register_t *resident_cpu);
void (*svc_system_off)(void);
void (*svc_system_reset)(void);
} spd_pm_ops_t;
/*
* Function prototype for the warmboot entrypoint function which will be
* programmed in the mailbox by the platform.
*/
typedef void (*mailbox_entrypoint_t)(void);
/******************************************************************************
* Structure to pass PSCI Library arguments.
*****************************************************************************/
typedef struct psci_lib_args {
/* The version information of PSCI Library Interface */
param_header_t h;
/* The warm boot entrypoint function */
mailbox_entrypoint_t mailbox_ep;
} psci_lib_args_t;
/* Helper macro to set the psci_lib_args_t structure at runtime */
#define SET_PSCI_LIB_ARGS_V1(_p, _entry) do { \
SET_PARAM_HEAD(_p, PARAM_PSCI_LIB_ARGS, VERSION_1, 0); \
(_p)->mailbox_ep = (_entry); \
} while (0)
/* Helper macro to define the psci_lib_args_t statically */
#define DEFINE_STATIC_PSCI_LIB_ARGS_V1(_name, _entry) \
static const psci_lib_args_t (_name) = { \
.h.type = (uint8_t)PARAM_PSCI_LIB_ARGS, \
.h.version = (uint8_t)VERSION_1, \
.h.size = (uint16_t)sizeof(_name), \
.h.attr = 0U, \
.mailbox_ep = (_entry) \
}
/* Helper macro to verify the pointer to psci_lib_args_t structure */
#define VERIFY_PSCI_LIB_ARGS_V1(_p) (((_p) != NULL) \
&& ((_p)->h.type == PARAM_PSCI_LIB_ARGS) \
&& ((_p)->h.version == VERSION_1) \
&& ((_p)->h.size == sizeof(*(_p))) \
&& ((_p)->h.attr == 0) \
&& ((_p)->mailbox_ep != NULL))
/******************************************************************************
* PSCI Library Interfaces
*****************************************************************************/
u_register_t psci_smc_handler(uint32_t smc_fid,
u_register_t x1,
u_register_t x2,
u_register_t x3,
u_register_t x4,
void *cookie,
void *handle,
u_register_t flags);
int psci_setup(const psci_lib_args_t *lib_args);
Introduce ARM SiP service to switch execution state In AArch64, privileged exception levels control the execution state (a.k.a. register width) of the immediate lower Exception Level; i.e. whether the lower exception level executes in AArch64 or AArch32 state. For an exception level to have its execution state changed at run time, it must request the change by raising a synchronous exception to the higher exception level. This patch implements and adds such a provision to the ARM SiP service, by which an immediate lower exception level can request to switch its execution state. The execution state is switched if the request is: - raised from non-secure world; - raised on the primary CPU, before any secondaries are brought online with CPU_ON PSCI call; - raised from an exception level immediately below EL3: EL2, if implemented; otherwise NS EL1. If successful, the SMC doesn't return to the caller, but to the entry point supplied with the call. Otherwise, the caller will observe the SMC returning with STATE_SW_E_DENIED code. If ARM Trusted Firmware is built for AArch32, the feature is not supported, and the call will always fail. For the ARM SiP service: - Add SMC function IDs for both AArch32 and AArch64; - Increment the SiP service minor version to 2; - Adjust the number of supported SiP service calls. Add documentation for ARM SiP service. Fixes ARM-software/tf-issues#436 Change-Id: I4347f2d6232e69fbfbe333b340fcd0caed0a4cea Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
2017-02-16 14:55:15 +00:00
int psci_secondaries_brought_up(void);
void psci_warmboot_entrypoint(void);
void psci_register_spd_pm_hook(const spd_pm_ops_t *pm);
void psci_prepare_next_non_secure_ctx(
entry_point_info_t *next_image_info);
#endif /* __ASSEMBLY__ */
#endif /* PSCI_LIB_H */