2019-05-29 05:03:58 +01:00
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/*
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Increase type widths to satisfy width requirements
Usually, C has no problem up-converting types to larger bit sizes. MISRA
rule 10.7 requires that you not do this, or be very explicit about this.
This resolves the following required rule:
bl1/aarch64/bl1_context_mgmt.c:81:[MISRA C-2012 Rule 10.7 (required)]<None>
The width of the composite expression "0U | ((mode & 3U) << 2U) | 1U |
0x3c0U" (32 bits) is less that the right hand operand
"18446744073709547519ULL" (64 bits).
This also resolves MISRA defects such as:
bl2/aarch64/bl2arch_setup.c:18:[MISRA C-2012 Rule 12.2 (required)]
In the expression "3U << 20", shifting more than 7 bits, the number
of bits in the essential type of the left expression, "3U", is
not allowed.
Further, MISRA requires that all shifts don't overflow. The definition of
PAGE_SIZE was (1U << 12), and 1U is 8 bits. This caused about 50 issues.
This fixes the violation by changing the definition to 1UL << 12. Since
this uses 32bits, it should not create any issues for aarch32.
This patch also contains a fix for a build failure in the sun50i_a64
platform. Specifically, these misra fixes removed a single and
instruction,
92407e73 and x19, x19, #0xffffffff
from the cm_setup_context function caused a relocation in
psci_cpus_on_start to require a linker-generated stub. This increased the
size of the .text section and caused an alignment later on to go over a
page boundary and round up to the end of RAM before placing the .data
section. This sectionn is of non-zero size and therefore causes a link
error.
The fix included in this reorders the functions during link time
without changing their ording with respect to alignment.
Change-Id: I76b4b662c3d262296728a8b9aab7a33b02087f16
Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>
2020-08-04 22:18:52 +01:00
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* Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
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2019-05-29 05:03:58 +01:00
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef ARM_TRUSTED_FIRMWARE_EXPORT_COMMON_EP_INFO_EXP_H
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#define ARM_TRUSTED_FIRMWARE_EXPORT_COMMON_EP_INFO_EXP_H
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/* EXPORT HEADER -- See include/export/README for details! -- EXPORT HEADER */
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#include "../lib/utils_def_exp.h"
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#include "param_header_exp.h"
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/*******************************************************************************
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* Constants that allow assembler code to access members of and the
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* 'entry_point_info' structure at their correct offsets.
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******************************************************************************/
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#define ENTRY_POINT_INFO_PC_OFFSET U(0x08)
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#ifdef __aarch64__
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#define ENTRY_POINT_INFO_ARGS_OFFSET U(0x18)
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#else
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#define ENTRY_POINT_INFO_LR_SVC_OFFSET U(0x10)
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#define ENTRY_POINT_INFO_ARGS_OFFSET U(0x14)
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#endif
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/* Security state of the image. */
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Increase type widths to satisfy width requirements
Usually, C has no problem up-converting types to larger bit sizes. MISRA
rule 10.7 requires that you not do this, or be very explicit about this.
This resolves the following required rule:
bl1/aarch64/bl1_context_mgmt.c:81:[MISRA C-2012 Rule 10.7 (required)]<None>
The width of the composite expression "0U | ((mode & 3U) << 2U) | 1U |
0x3c0U" (32 bits) is less that the right hand operand
"18446744073709547519ULL" (64 bits).
This also resolves MISRA defects such as:
bl2/aarch64/bl2arch_setup.c:18:[MISRA C-2012 Rule 12.2 (required)]
In the expression "3U << 20", shifting more than 7 bits, the number
of bits in the essential type of the left expression, "3U", is
not allowed.
Further, MISRA requires that all shifts don't overflow. The definition of
PAGE_SIZE was (1U << 12), and 1U is 8 bits. This caused about 50 issues.
This fixes the violation by changing the definition to 1UL << 12. Since
this uses 32bits, it should not create any issues for aarch32.
This patch also contains a fix for a build failure in the sun50i_a64
platform. Specifically, these misra fixes removed a single and
instruction,
92407e73 and x19, x19, #0xffffffff
from the cm_setup_context function caused a relocation in
psci_cpus_on_start to require a linker-generated stub. This increased the
size of the .text section and caused an alignment later on to go over a
page boundary and round up to the end of RAM before placing the .data
section. This sectionn is of non-zero size and therefore causes a link
error.
The fix included in this reorders the functions during link time
without changing their ording with respect to alignment.
Change-Id: I76b4b662c3d262296728a8b9aab7a33b02087f16
Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>
2020-08-04 22:18:52 +01:00
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#define EP_SECURITY_MASK UL(0x1)
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#define EP_SECURITY_SHIFT UL(0)
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#define EP_SECURE UL(0x0)
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#define EP_NON_SECURE UL(0x1)
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2019-05-29 05:03:58 +01:00
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/* Endianness of the image. */
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#define EP_EE_MASK U(0x2)
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#define EP_EE_SHIFT U(1)
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#define EP_EE_LITTLE U(0x0)
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#define EP_EE_BIG U(0x2)
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#define EP_GET_EE(x) ((x) & EP_EE_MASK)
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#define EP_SET_EE(x, ee) ((x) = ((x) & ~EP_EE_MASK) | (ee))
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/* Enable or disable access to the secure timer from secure images. */
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#define EP_ST_MASK U(0x4)
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#define EP_ST_SHIFT U(2)
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#define EP_ST_DISABLE U(0x0)
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#define EP_ST_ENABLE U(0x4)
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#define EP_GET_ST(x) ((x) & EP_ST_MASK)
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#define EP_SET_ST(x, ee) ((x) = ((x) & ~EP_ST_MASK) | (ee))
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/* Determine if an image is executable or not. */
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#define EP_EXE_MASK U(0x8)
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#define EP_EXE_SHIFT U(3)
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#define EP_NON_EXECUTABLE U(0x0)
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#define EP_EXECUTABLE U(0x8)
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#define EP_GET_EXE(x) ((x) & EP_EXE_MASK)
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#define EP_SET_EXE(x, ee) ((x) = ((x) & ~EP_EXE_MASK) | (ee))
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/* Flag to indicate the first image that is executed. */
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#define EP_FIRST_EXE_MASK U(0x10)
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#define EP_FIRST_EXE_SHIFT U(4)
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#define EP_FIRST_EXE U(0x10)
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#define EP_GET_FIRST_EXE(x) ((x) & EP_FIRST_EXE_MASK)
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#define EP_SET_FIRST_EXE(x, ee) ((x) = ((x) & ~EP_FIRST_EXE_MASK) | (ee))
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#ifndef __ASSEMBLER__
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typedef struct aapcs64_params {
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uint64_t arg0;
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uint64_t arg1;
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uint64_t arg2;
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uint64_t arg3;
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uint64_t arg4;
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uint64_t arg5;
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uint64_t arg6;
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uint64_t arg7;
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} aapcs64_params_t;
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typedef struct aapcs32_params {
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uint32_t arg0;
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uint32_t arg1;
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uint32_t arg2;
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uint32_t arg3;
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} aapcs32_params_t;
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/*****************************************************************************
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* This structure represents the superset of information needed while
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* switching exception levels. The only two mechanisms to do so are
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* ERET & SMC. Security state is indicated using bit zero of header
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* attribute
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* NOTE: BL1 expects entrypoint followed by spsr at an offset from the start
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* of this structure defined by the macro `ENTRY_POINT_INFO_PC_OFFSET` while
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* processing SMC to jump to BL31.
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*****************************************************************************/
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typedef struct entry_point_info {
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param_header_t h;
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uintptr_t pc;
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uint32_t spsr;
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#ifdef __aarch64__
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aapcs64_params_t args;
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#else
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uintptr_t lr_svc;
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aapcs32_params_t args;
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#endif
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} entry_point_info_t;
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#endif /*__ASSEMBLER__*/
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#endif /* ARM_TRUSTED_FIRMWARE_EXPORT_COMMON_EP_INFO_EXP_H */
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