2017-02-24 08:26:11 +00:00
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/*
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* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
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*
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2017-05-03 09:38:09 +01:00
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* SPDX-License-Identifier: BSD-3-Clause
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2017-02-24 08:26:11 +00:00
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*/
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2018-11-08 10:20:19 +00:00
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#ifndef ADDRESSMAP_SHARED_H
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#define ADDRESSMAP_SHARED_H
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2017-02-24 08:26:11 +00:00
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#define SIZE_K(n) ((n) * 1024)
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#define SIZE_M(n) ((n) * 1024 * 1024)
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rockchip/rk3399: enable PMU_PERILP_PD_EN bit when suspend
with PMU_PERILP_PD_EN bit enable, the soc will shutdown
cm0, crypto, dcf, imem(normal SRAM), dmac, bootrom, efuse_con,
spi, i2c, uart, saradc, tsadc when suspend, we have M0 code
need to run when suspend in normal SRAM, so we need to take
care of that.
Change-Id: I8c066637e5b81d4b1d53197450b9d592cbe00793
Signed-off-by: Lin Huang <hl@rock-chips.com>
Signed-off-by: Derek Basehore <dbasehore@chromium.org>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
2017-05-16 09:40:46 +01:00
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#define SRAM_TEXT_LIMIT (4 * 1024)
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#define SRAM_DATA_LIMIT (4 * 1024)
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#define SRAM_BIN_LIMIT (4 * 1024)
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2017-02-24 08:26:11 +00:00
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/*
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* The parts of the shared defined registers address with AP and M0,
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* let's note and mark the previous defines like this:
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*/
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#define GIC500_BASE (MMIO_BASE + 0x06E00000)
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#define UART0_BASE (MMIO_BASE + 0x07180000)
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#define UART1_BASE (MMIO_BASE + 0x07190000)
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#define UART2_BASE (MMIO_BASE + 0x071A0000)
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#define UART3_BASE (MMIO_BASE + 0x071B0000)
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#define PMU_BASE (MMIO_BASE + 0x07310000)
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#define PMUGRF_BASE (MMIO_BASE + 0x07320000)
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#define SGRF_BASE (MMIO_BASE + 0x07330000)
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#define PMUSRAM_BASE (MMIO_BASE + 0x073B0000)
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#define PWM_BASE (MMIO_BASE + 0x07420000)
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#define CIC_BASE (MMIO_BASE + 0x07620000)
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#define PD_BUS0_BASE (MMIO_BASE + 0x07650000)
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#define DCF_BASE (MMIO_BASE + 0x076A0000)
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#define GPIO0_BASE (MMIO_BASE + 0x07720000)
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#define GPIO1_BASE (MMIO_BASE + 0x07730000)
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#define PMUCRU_BASE (MMIO_BASE + 0x07750000)
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#define CRU_BASE (MMIO_BASE + 0x07760000)
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#define GRF_BASE (MMIO_BASE + 0x07770000)
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#define GPIO2_BASE (MMIO_BASE + 0x07780000)
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#define GPIO3_BASE (MMIO_BASE + 0x07788000)
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#define GPIO4_BASE (MMIO_BASE + 0x07790000)
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2017-05-18 11:04:25 +01:00
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#define WDT1_BASE (MMIO_BASE + 0x07840000)
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#define WDT0_BASE (MMIO_BASE + 0x07848000)
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#define TIMER_BASE (MMIO_BASE + 0x07850000)
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2017-02-24 08:26:11 +00:00
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#define STIME_BASE (MMIO_BASE + 0x07860000)
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#define SRAM_BASE (MMIO_BASE + 0x078C0000)
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#define SERVICE_NOC_0_BASE (MMIO_BASE + 0x07A50000)
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#define DDRC0_BASE (MMIO_BASE + 0x07A80000)
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#define SERVICE_NOC_1_BASE (MMIO_BASE + 0x07A84000)
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#define DDRC1_BASE (MMIO_BASE + 0x07A88000)
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#define SERVICE_NOC_2_BASE (MMIO_BASE + 0x07A8C000)
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#define SERVICE_NOC_3_BASE (MMIO_BASE + 0x07A90000)
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#define CCI500_BASE (MMIO_BASE + 0x07B00000)
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#define COLD_BOOT_BASE (MMIO_BASE + 0x07FF0000)
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/* Registers size */
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#define GIC500_SIZE SIZE_M(2)
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#define UART0_SIZE SIZE_K(64)
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#define UART1_SIZE SIZE_K(64)
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#define UART2_SIZE SIZE_K(64)
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#define UART3_SIZE SIZE_K(64)
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#define PMU_SIZE SIZE_K(64)
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#define PMUGRF_SIZE SIZE_K(64)
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#define SGRF_SIZE SIZE_K(64)
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#define PMUSRAM_SIZE SIZE_K(64)
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#define PMUSRAM_RSIZE SIZE_K(8)
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#define PWM_SIZE SIZE_K(64)
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#define CIC_SIZE SIZE_K(4)
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#define DCF_SIZE SIZE_K(4)
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#define GPIO0_SIZE SIZE_K(64)
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#define GPIO1_SIZE SIZE_K(64)
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#define PMUCRU_SIZE SIZE_K(64)
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#define CRU_SIZE SIZE_K(64)
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#define GRF_SIZE SIZE_K(64)
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#define GPIO2_SIZE SIZE_K(32)
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#define GPIO3_SIZE SIZE_K(32)
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#define GPIO4_SIZE SIZE_K(32)
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#define STIME_SIZE SIZE_K(64)
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#define SRAM_SIZE SIZE_K(192)
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#define SERVICE_NOC_0_SIZE SIZE_K(192)
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#define DDRC0_SIZE SIZE_K(32)
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#define SERVICE_NOC_1_SIZE SIZE_K(16)
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#define DDRC1_SIZE SIZE_K(32)
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#define SERVICE_NOC_2_SIZE SIZE_K(16)
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#define SERVICE_NOC_3_SIZE SIZE_K(448)
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#define CCI500_SIZE SIZE_M(1)
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#define PD_BUS0_SIZE SIZE_K(448)
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/* DDR Registers address */
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#define CTL_BASE(ch) (DDRC0_BASE + (ch) * 0x8000)
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#define CTL_REG(ch, n) (CTL_BASE(ch) + (n) * 0x4)
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#define PI_OFFSET 0x800
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#define PI_BASE(ch) (CTL_BASE(ch) + PI_OFFSET)
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#define PI_REG(ch, n) (PI_BASE(ch) + (n) * 0x4)
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#define PHY_OFFSET 0x2000
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#define PHY_BASE(ch) (CTL_BASE(ch) + PHY_OFFSET)
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#define PHY_REG(ch, n) (PHY_BASE(ch) + (n) * 0x4)
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#define MSCH_BASE(ch) (SERVICE_NOC_1_BASE + (ch) * 0x8000)
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2018-11-08 10:20:19 +00:00
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#endif /* ADDRESSMAP_SHARED_H */
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