arm-trusted-firmware/plat/arm/board/corstone700/drivers/mhu/mhu.c

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Corstone700: add support for mhuv2 in arm TF-A Note: This patch implements in-band messaging protocol only. ARM has launched a next version of MHU i.e. MHUv2 with its latest subsystems. The main change is that the MHUv2 is now a distributed IP with different peripheral views (registers) for the sender and receiver. Another main difference is that MHUv1 duplex channels are now split into simplex/half duplex in MHUv2. MHUv2 has a configurable number of communication channels. There is a capability register (MSG_NO_CAP) to find out how many channels are available in a system. The register offsets have also changed for STAT, SET & CLEAR registers from 0x0, 0x8 & 0x10 in MHUv1 to 0x0, 0xC & 0x8 in MHUv2 respectively. 0x0 0x4 0x8 0xC 0x1F ------------------------....----- | STAT | | | SET | | | ------------------------....----- Transmit Channel 0x0 0x4 0x8 0xC 0x1F ------------------------....----- | STAT | | CLR | | | | ------------------------....----- Receive Channel The MHU controller can request the receiver to wake-up and once the request is removed, the receiver may go back to sleep, but the MHU itself does not actively put a receiver to sleep. So, in order to wake-up the receiver when the sender wants to send data, the sender has to set ACCESS_REQUEST register first in order to wake-up receiver, state of which can be detected using ACCESS_READY register. ACCESS_REQUEST has an offset of 0xF88 & ACCESS_READY has an offset of 0xF8C and are accessible only on any sender channel. This patch adds necessary changes in a new file required to support the latest MHUv2 controller. This patch also needs an update in DT binding for ARM MHUv2 as we need a second register base (tx base) which would be used as the send channel base. Change-Id: I1455e08b3d88671a191c558790c503eabe07a8e6 Signed-off-by: Tushar Khandelwal <tushar.khandelwal@arm.com>
2020-01-29 16:51:42 +00:00
/*
* Copyright (c) 2019-2020, ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <assert.h>
#include <arch_helpers.h>
#include <common/debug.h>
#include <drivers/delay_timer.h>
#include <lib/bakery_lock.h>
#include <lib/mmio.h>
#include "mhu.h"
#include <plat_arm.h>
#include <platform_def.h>
ARM_INSTANTIATE_LOCK;
#pragma weak plat_arm_pwrc_setup
/*
* Slot 31 is reserved because the MHU hardware uses this register bit to
* indicate a non-secure access attempt. The total number of available slots is
* therefore 31 [30:0].
*/
#define MHU_MAX_SLOT_ID 30
void mhu_secure_message_start(uintptr_t address, unsigned int slot_id)
{
unsigned int intr_stat_check;
uint64_t timeout_cnt;
volatile uint8_t expiration;
assert(slot_id <= MHU_MAX_SLOT_ID);
arm_lock_get();
/*
* Make sure any previous command has finished
* and polling timeout not expired
*/
timeout_cnt = timeout_init_us(MHU_POLL_INTR_STAT_TIMEOUT);
do {
intr_stat_check = (mmio_read_32(address + CPU_INTR_S_STAT) &
(1 << slot_id));
expiration = timeout_elapsed(timeout_cnt);
} while ((intr_stat_check != 0U) && (expiration == 0U));
/*
* Note: No risk of timer overflows while waiting
* for the timeout expiration.
* According to Armv8 TRM: System counter roll-over
* time of not less than 40 years
*/
}
void mhu_secure_message_send(uintptr_t address,
unsigned int slot_id,
unsigned int message)
{
unsigned char access_ready;
uint64_t timeout_cnt;
volatile uint8_t expiration;
assert(slot_id <= MHU_MAX_SLOT_ID);
assert((mmio_read_32(address + CPU_INTR_S_STAT) &
(1 << slot_id)) == 0U);
MHU_V2_ACCESS_REQUEST(address);
timeout_cnt = timeout_init_us(MHU_POLL_INTR_STAT_TIMEOUT);
do {
access_ready = MHU_V2_IS_ACCESS_READY(address);
expiration = timeout_elapsed(timeout_cnt);
} while ((access_ready == 0U) && (expiration == 0U));
/*
* Note: No risk of timer overflows while waiting
* for the timeout expiration.
* According to Armv8 TRM: System counter roll-over
* time of not less than 40 years
*/
mmio_write_32(address + CPU_INTR_S_SET, message);
}
void mhu_secure_message_end(uintptr_t address, unsigned int slot_id)
{
assert(slot_id <= MHU_MAX_SLOT_ID);
/*
* Clear any response we got by writing one in the relevant slot bit to
* the CLEAR register
*/
MHU_V2_CLEAR_REQUEST(address);
arm_lock_release();
}
void __init mhu_secure_init(void)
{
arm_lock_init();
/*
* The STAT register resets to zero. Ensure it is in the expected state,
* as a stale or garbage value would make us think it's a message we've
* already sent.
*/
assert(mmio_read_32(PLAT_SDK700_MHU0_SEND + CPU_INTR_S_STAT) == 0);
}