2017-06-28 09:11:31 +01:00
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/*
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* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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2018-11-08 10:20:19 +00:00
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#ifndef HI3798CV200_H
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#define HI3798CV200_H
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2017-06-28 09:11:31 +01:00
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2018-12-14 00:18:21 +00:00
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#include <lib/utils_def.h>
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2018-01-02 16:53:08 +00:00
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2017-06-28 09:11:31 +01:00
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/* PL011 */
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#define PL011_UART0_BASE (0xF8B00000)
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#define PL011_BAUDRATE (115200)
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#define PL011_UART0_CLK_IN_HZ (75000000)
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/* Sys Counter */
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#define SYS_COUNTER_FREQ_IN_TICKS (24000000)
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#define SYS_COUNTER_FREQ_IN_MHZ (24)
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/* Timer */
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#define SEC_TIMER0_BASE (0xF8008000)
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#define TIMER00_LOAD (SEC_TIMER0_BASE + 0x000)
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#define TIMER00_VALUE (SEC_TIMER0_BASE + 0x004)
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#define TIMER00_CONTROL (SEC_TIMER0_BASE + 0x008)
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#define TIMER00_BGLOAD (SEC_TIMER0_BASE + 0x018)
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#define SEC_TIMER2_BASE (0xF8009000)
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#define TIMER20_LOAD (SEC_TIMER2_BASE + 0x000)
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#define TIMER20_VALUE (SEC_TIMER2_BASE + 0x004)
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#define TIMER20_CONTROL (SEC_TIMER2_BASE + 0x008)
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#define TIMER20_BGLOAD (SEC_TIMER2_BASE + 0x018)
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/* GPIO */
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2017-10-19 08:49:52 +01:00
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#define GPIO_MAX (13)
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2017-06-28 09:11:31 +01:00
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#define GPIO_BASE(x) (x != 5 ? \
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0xf820000 + x * 0x1000 : 0xf8004000)
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/* SCTL */
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#define REG_BASE_SCTL (0xF8000000)
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#define REG_SC_GEN12 (0x00B0)
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/* CRG */
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#define REG_BASE_CRG (0xF8A22000)
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#define REG_CPU_LP (0x48)
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#define REG_CPU_RST (0x50)
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#define REG_PERI_CRG39 (0x9C)
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#define REG_PERI_CRG40 (0xA0)
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/* MCI */
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#define REG_BASE_MCI (0xF9830000)
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#define MCI_CDETECT (0x50)
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#define MCI_VERID (0x6C)
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#define MCI_VERID_VALUE (0x5342250A)
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#define MCI_VERID_VALUE2 (0x5342270A)
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/* EMMC */
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#define REG_EMMC_PERI_CRG REG_PERI_CRG40
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#define REG_SDCARD_PERI_CRG REG_PERI_CRG39
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#define EMMC_CLK_MASK (0x7 << 8)
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#define EMMC_SRST_REQ (0x1 << 4)
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#define EMMC_CKEN (0x1 << 1)
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#define EMMC_BUS_CKEN (0x1 << 0)
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#define EMMC_CLK_100M (0 << 8)
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#define EMMC_CLK_50M (1 << 8)
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#define EMMC_CLK_25M (2 << 8)
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2018-01-02 16:53:08 +00:00
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#define EMMC_DESC_SIZE U(0x00100000) /* 1MB */
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2017-06-28 09:11:31 +01:00
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#define EMMC_INIT_PARAMS(base) \
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2018-08-04 11:07:26 +01:00
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{ .bus_width = MMC_BUS_WIDTH_8, \
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2017-06-28 09:11:31 +01:00
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.clk_rate = 25 * 1000 * 1000, \
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2018-01-02 16:53:08 +00:00
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.desc_base = (base), \
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2017-06-28 09:11:31 +01:00
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.desc_size = EMMC_DESC_SIZE, \
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2018-08-04 11:07:26 +01:00
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.flags = MMC_FLAG_CMD23, \
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2017-06-28 09:11:31 +01:00
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.reg_base = REG_BASE_MCI, \
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}
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/* GIC-400 */
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#define GICD_BASE (0xF1001000)
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#define GICC_BASE (0xF1002000)
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#define GICR_BASE (0xF1000000)
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/* FIQ platform related define */
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#define HISI_IRQ_SEC_SGI_0 8
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#define HISI_IRQ_SEC_SGI_1 9
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#define HISI_IRQ_SEC_SGI_2 10
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#define HISI_IRQ_SEC_SGI_3 11
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#define HISI_IRQ_SEC_SGI_4 12
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#define HISI_IRQ_SEC_SGI_5 13
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#define HISI_IRQ_SEC_SGI_6 14
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#define HISI_IRQ_SEC_SGI_7 15
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#define HISI_IRQ_SEC_PPI_0 29
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#define HISI_IRQ_SEC_TIMER0 60
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#define HISI_IRQ_SEC_TIMER1 50
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#define HISI_IRQ_SEC_TIMER2 52
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#define HISI_IRQ_SEC_TIMER3 88
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#define HISI_IRQ_SEC_AXI 110
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/* Watchdog */
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#define HISI_WDG0_BASE (0xF8A2C000)
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2017-08-28 11:55:43 +01:00
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#define HISI_TZPC_BASE (0xF8A80000)
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#define HISI_TZPC_SEC_ATTR_CTRL (HISI_TZPC_BASE + 0x10)
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2018-11-08 10:20:19 +00:00
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#endif /* HI3798CV200_H */
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